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-rw-r--r--usrp2/top/u2_rev3/Makefile4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 99effb038..05ada2476 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -6,7 +6,7 @@
# Project Setup
##################################################
TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build-udp$(ISE))
+BUILD_DIR = $(abspath build)
##################################################
# Include other makefiles
@@ -46,7 +46,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
# Sources
##################################################
TOP_SRCS = \
-u2_core_udp.v \
+u2_core.v \
u2_rev3.v \
u2_rev3.ucf