summaryrefslogtreecommitdiffstats
path: root/usrp2/top/u1plus
diff options
context:
space:
mode:
Diffstat (limited to 'usrp2/top/u1plus')
-rw-r--r--usrp2/top/u1plus/.gitignore1
-rw-r--r--usrp2/top/u1plus/Makefile232
-rw-r--r--usrp2/top/u1plus/timing.ucf2
-rw-r--r--usrp2/top/u1plus/u1plus.ucf203
-rw-r--r--usrp2/top/u1plus/u1plus.v141
5 files changed, 579 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/.gitignore b/usrp2/top/u1plus/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/usrp2/top/u1plus/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile
new file mode 100644
index 000000000..8a7c7856d
--- /dev/null
+++ b/usrp2/top/u1plus/Makefile
@@ -0,0 +1,232 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u1plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan3A" \
+device XC3S1400A \
+package ft256 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/priority_enc.v \
+control_lib/pic.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u1_core/u1_core.v \
+top/u1plus/u1plus.ucf \
+top/u1plus/timing.ucf \
+top/u1plus/u1plus.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf
new file mode 100644
index 000000000..ca5ebf8e3
--- /dev/null
+++ b/usrp2/top/u1plus/timing.ucf
@@ -0,0 +1,2 @@
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/u1plus/u1plus.ucf
new file mode 100644
index 000000000..8a22d0966
--- /dev/null
+++ b/usrp2/top/u1plus/u1plus.ucf
@@ -0,0 +1,203 @@
+## Main Clock
+NET "CLK_FPGA_P" LOC = "R7" ;
+NET "CLK_FPGA_N" LOC = "T7" ;
+
+## UART
+NET "FPGA_TXD" LOC = "H16" ;
+NET "FPGA_RXD" LOC = "H12" ;
+
+## I2C
+NET "SDA_FPGA" LOC = "T13" ;
+NET "SCL_FPGA" LOC = "R13" ;
+
+## CGEN
+NET "cgen_st_ld" LOC = "M13" ;
+NET "cgen_st_refmon" LOC = "J14" ;
+NET "cgen_st_status" LOC = "P6" ;
+NET "cgen_ref_sel" LOC = "T2" ;
+NET "cgen_sync_b" LOC = "H15" ;
+
+## FPGA Config
+NET "fpga_cfg_din" LOC = "T14" ;
+NET "fpga_cfg_cclk" LOC = "R14" ;
+NET "fpga_cfg_init_b" LOC = "T12" ;
+
+## MISC
+NET "mystery_bus<2>" LOC = "T11" ;
+NET "mystery_bus<1>" LOC = "C4" ;
+NET "mystery_bus<0>" LOC = "E7" ;
+NET "reset_n" LOC = "D5" ;
+NET "PPS_IN" LOC = "M14" ;
+NET "reset_codec" LOC = "B14" ;
+
+## GPIF
+NET "GPIF_D<15>" LOC = "P7" ;
+NET "GPIF_D<14>" LOC = "N8" ;
+NET "GPIF_D<13>" LOC = "T5" ;
+NET "GPIF_D<12>" LOC = "T6" ;
+NET "GPIF_D<11>" LOC = "N6" ;
+NET "GPIF_D<10>" LOC = "P5" ;
+NET "GPIF_D<9>" LOC = "R3" ;
+NET "GPIF_D<8>" LOC = "T3" ;
+NET "GPIF_D<7>" LOC = "N12" ;
+NET "GPIF_D<6>" LOC = "P13" ;
+NET "GPIF_D<5>" LOC = "P11" ;
+NET "GPIF_D<4>" LOC = "R9" ;
+NET "GPIF_D<3>" LOC = "T9" ;
+NET "GPIF_D<2>" LOC = "N9" ;
+NET "GPIF_D<1>" LOC = "P9" ;
+NET "GPIF_D<0>" LOC = "P8" ;
+
+NET "GPIF_CTL<3>" LOC = "N5" ;
+NET "GPIF_CTL<2>" LOC = "M11" ;
+NET "GPIF_CTL<1>" LOC = "M9" ;
+NET "GPIF_CTL<0>" LOC = "M7" ;
+
+NET "GPIF_RDY<3>" LOC = "N11" ;
+NET "GPIF_RDY<2>" LOC = "T10" ;
+NET "GPIF_RDY<1>" LOC = "T4" ;
+NET "GPIF_RDY<0>" LOC = "R5" ;
+
+NET "FX2_PA7_FLAGD" LOC = "P12" ;
+NET "FX2_PA6_PKTEND" LOC = "R11" ;
+NET "FX2_PA2_SLOE" LOC = "P10" ;
+
+NET "IFCLK" LOC = "T8" ;
+
+## LEDs
+NET "debug_led<2>" LOC = "R2" ;
+NET "debug_led<1>" LOC = "N4" ;
+NET "debug_led<0>" LOC = "P4" ;
+
+## Debug bus
+NET "debug_clk<0>" LOC = "K15" ;
+NET "debug_clk<1>" LOC = "K14" ;
+NET "debug<0>" LOC = "K16" ;
+NET "debug<1>" LOC = "J16" ;
+NET "debug<2>" LOC = "C16" ;
+NET "debug<3>" LOC = "C15" ;
+NET "debug<4>" LOC = "E13" ;
+NET "debug<5>" LOC = "D14" ;
+NET "debug<6>" LOC = "D16" ;
+NET "debug<7>" LOC = "D15" ;
+NET "debug<8>" LOC = "E14" ;
+NET "debug<9>" LOC = "F13" ;
+NET "debug<10>" LOC = "G13" ;
+NET "debug<11>" LOC = "F14" ;
+NET "debug<12>" LOC = "E16" ;
+NET "debug<13>" LOC = "F15" ;
+NET "debug<14>" LOC = "H13" ;
+NET "debug<15>" LOC = "G14" ;
+NET "debug<16>" LOC = "G16" ;
+NET "debug<17>" LOC = "F16" ;
+NET "debug<18>" LOC = "J12" ;
+NET "debug<19>" LOC = "J13" ;
+NET "debug<20>" LOC = "L14" ;
+NET "debug<21>" LOC = "L16" ;
+NET "debug<22>" LOC = "M15" ;
+NET "debug<23>" LOC = "M16" ;
+NET "debug<24>" LOC = "L13" ;
+NET "debug<25>" LOC = "K13" ;
+NET "debug<26>" LOC = "P16" ;
+NET "debug<27>" LOC = "N16" ;
+NET "debug<28>" LOC = "R15" ;
+NET "debug<29>" LOC = "P15" ;
+NET "debug<30>" LOC = "N13" ;
+NET "debug<31>" LOC = "N14" ;
+
+## ADC
+NET "adc<11>" LOC = "B15" ;
+NET "adc<10>" LOC = "A8" ;
+NET "adc<9>" LOC = "B8" ;
+NET "adc<8>" LOC = "C8" ;
+NET "adc<7>" LOC = "D8" ;
+NET "adc<6>" LOC = "C9" ;
+NET "adc<5>" LOC = "A9" ;
+NET "adc<4>" LOC = "C10" ;
+NET "adc<3>" LOC = "D9" ;
+NET "adc<2>" LOC = "A3" ;
+NET "adc<1>" LOC = "B3" ;
+NET "adc<0>" LOC = "A4" ;
+NET "RXSYNC" LOC = "D10" ;
+
+## DAC
+NET "TXBLANK" LOC = "K1" ;
+NET "TXSYNC" LOC = "J2" ;
+NET "dac<0>" LOC = "J1" ;
+NET "dac<1>" LOC = "H3" ;
+NET "dac<2>" LOC = "J3" ;
+NET "dac<3>" LOC = "G2" ;
+NET "dac<4>" LOC = "H1" ;
+NET "dac<5>" LOC = "N3" ;
+NET "dac<6>" LOC = "M4" ;
+NET "dac<7>" LOC = "R1" ;
+NET "dac<8>" LOC = "P2" ;
+NET "dac<9>" LOC = "P1" ;
+NET "dac<10>" LOC = "M1" ;
+NET "dac<11>" LOC = "N1" ;
+NET "dac<12>" LOC = "M3" ;
+NET "dac<13>" LOC = "L4" ;
+
+## TX DB
+NET "io_tx<0>" LOC = "K4" ;
+NET "io_tx<1>" LOC = "L3" ;
+NET "io_tx<2>" LOC = "L2" ;
+NET "io_tx<3>" LOC = "F1" ;
+NET "io_tx<4>" LOC = "F3" ;
+NET "io_tx<5>" LOC = "G3" ;
+NET "io_tx<6>" LOC = "E3" ;
+NET "io_tx<7>" LOC = "E2" ;
+NET "io_tx<8>" LOC = "E4" ;
+NET "io_tx<9>" LOC = "F4" ;
+NET "io_tx<10>" LOC = "D1" ;
+NET "io_tx<11>" LOC = "E1" ;
+NET "io_tx<12>" LOC = "D4" ;
+NET "io_tx<13>" LOC = "D3" ;
+NET "io_tx<14>" LOC = "C2" ;
+NET "io_tx<15>" LOC = "C1" ;
+
+## RX DB
+NET "io_rx<0>" LOC = "D7" ;
+NET "io_rx<1>" LOC = "C6" ;
+NET "io_rx<2>" LOC = "A6" ;
+NET "io_rx<3>" LOC = "B6" ;
+NET "io_rx<4>" LOC = "E9" ;
+NET "io_rx<5>" LOC = "A7" ;
+NET "io_rx<6>" LOC = "C7" ;
+NET "io_rx<7>" LOC = "B10" ;
+NET "io_rx<8>" LOC = "A10" ;
+NET "io_rx<9>" LOC = "C11" ;
+NET "io_rx<10>" LOC = "A11" ;
+NET "io_rx<11>" LOC = "D11" ;
+NET "io_rx<12>" LOC = "B12" ;
+NET "io_rx<13>" LOC = "A12" ;
+NET "io_rx<14>" LOC = "A14" ;
+NET "io_rx<15>" LOC = "A13" ;
+
+## SPI
+NET "SEN_AUX" LOC = "C12" ;
+NET "SCLK_AUX" LOC = "D12" ;
+NET "MISO_AUX" LOC = "J5" ;
+NET "SCLK_CODEC" LOC = "K3" ;
+NET "SEN_CODEC" LOC = "D13" ;
+NET "MOSI_CODEC" LOC = "C13" ;
+NET "MISO_CODEC" LOC = "G4" ;
+
+NET "MISO_RX_DB" LOC = "E6" ;
+NET "SEN_RX_DB" LOC = "B4" ;
+NET "MOSI_RX_DB" LOC = "A5" ;
+NET "SCLK_RX_DB" LOC = "C5" ;
+
+NET "MISO_TX_DB" LOC = "J4" ;
+NET "SEN_TX_DB" LOC = "N2" ;
+NET "MOSI_TX_DB" LOC = "L1" ;
+NET "SCLK_TX_DB" LOC = "G1" ;
+
+## Dedicated pins
+#NET "TMS" LOC = "B2" ;
+#NET "TDO" LOC = "B16" ;
+#NET "TDI" LOC = "B1" ;
+#NET "TCK" LOC = "A15" ;
+
+##NET "fpga_cfg_prog_b" LOC = "A2" ;
+##NET "fpga_cfg_done" LOC = "T15" ;
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v
new file mode 100644
index 000000000..cb5fbdd36
--- /dev/null
+++ b/usrp2/top/u1plus/u1plus.v
@@ -0,0 +1,141 @@
+
+module u1plus
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Main Clock
+ output FPGA_TXD, input FPGA_RXD, // UART
+ inout SDA_FPGA, inout SCL_FPGA, // I2C
+
+ // CGEN
+ input cgen_st_ld,
+ input cgen_st_refmon,
+ input cgen_st_status,
+ input cgen_ref_sel,
+ input cgen_sync_b,
+
+ // FPGA Config
+ input fpga_cfg_din,
+ input fpga_cfg_cclk,
+ input fpga_cfg_init_b,
+
+ // MISC
+ input [2:0] mystery_bus,
+ input reset_n,
+ input PPS_IN,
+ output reset_codec,
+
+ // GPIF
+ inout [15:0] GPIF_D,
+ input [3:0] GPIF_CTL,
+ output [3:0] GPIF_RDY,
+ input FX2_PA7_FLAGD,
+ input FX2_PA6_PKTEND,
+ input FX2_PA2_SLOE,
+ input IFCLK,
+
+ output [2:0] debug_led,
+
+ // Debug bus
+ output [1:0] debug_clk,
+ output [31:0] debug,
+
+ input [11:0] adc,
+ input RXSYNC,
+
+ output TXBLANK,
+ output TXSYNC,
+ output [13:0] dac,
+
+ // TX DB
+ inout [15:0] io_tx,
+ inout [15:0] io_rx,
+
+ // SPI
+ output SEN_AUX, output SCLK_AUX, input MISO_AUX,
+ output SEN_CODEC, output SCLK_CODEC, output MOSI_CODEC, input MISO_CODEC,
+ output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
+ output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB
+ );
+
+ wire clk_fpga, sys_clk, wb_clk, dcm_out, clk_div, dcm_locked;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ DCM DCM_INST (.CLKFB(sys_clk),
+ .CLKIN(clk_fpga),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(dcm_locked),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 15.625;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG sysclk_BUFG (.I(dcm_out), .O(sys_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ wire mosi, miso, sclk;
+ assign SCLK_AUX = ~SEN_AUX ? sclk : 2'b00;
+ assign {SCLK_CODEC,MOSI_CODEC} = ~SEN_CODEC ? {sclk,mosi} : 2'b00;
+ assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'b00;
+ assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'b00;
+ assign miso = (~SEN_CODEC & MISO_CODEC) | (~SEN_AUX & MISO_AUX) |
+ (~SEN_RX_DB & MISO_RX_DB) |(~SEN_TX_DB & MISO_TX_DB);
+
+ u1_core u1_core
+ (.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .wb_clk(wb_clk), .wb_rst(wb_rst),
+ .uart_tx_o(FPGA_TXD), .uart_rx_i(FPGA_RXD), .uart_baud_o(),
+
+ .leds(debug_led), .debug(debug), .debug_clk(debug_clk),
+
+ .scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_pad_oen_o(scl_pad_oen_o),
+ .sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_pad_oen_o(sda_pad_oen_o),
+
+ .pps(PPS_IN),
+ .reset_codec(reset_codec),
+
+ // GPIF
+ .gpif_clk(IFCLK), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
+ .gpif_misc({FX2_PA7_FLAGD, FX2_PA6_PKTEND, FX2_PA2_SLOE}),
+
+ .adc(adc), .rxsync(RXSYNC),
+
+ .txblank(TXBLANK), .txsync(TXSYNC), .dac(dac),
+
+ .io_tx(io_tx), .io_rx(io_rx),
+
+ // SPI
+ .sclk(sclk), .mosi(mosi), .miso(miso), .sen({SEN_AUX, SEN_CODEC, SEN_RX_DB, SEN_TX_DB}),
+ .sim_mode(0)
+ );
+
+endmodule // u1plus
+
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 08:17:56 +0000