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-rw-r--r--usrp2/top/u1plus/u1plus.v254
1 files changed, 133 insertions, 121 deletions
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v
index cb5fbdd36..6ed478420 100644
--- a/usrp2/top/u1plus/u1plus.v
+++ b/usrp2/top/u1plus/u1plus.v
@@ -1,141 +1,153 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
module u1plus
- (input CLK_FPGA_P, input CLK_FPGA_N, // Main Clock
- output FPGA_TXD, input FPGA_RXD, // UART
- inout SDA_FPGA, inout SCL_FPGA, // I2C
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ output FPGA_TXD, input FPGA_RXD,
- // CGEN
- input cgen_st_ld,
- input cgen_st_refmon,
- input cgen_st_status,
- input cgen_ref_sel,
- input cgen_sync_b,
-
- // FPGA Config
- input fpga_cfg_din,
- input fpga_cfg_cclk,
- input fpga_cfg_init_b,
-
- // MISC
- input [2:0] mystery_bus,
- input reset_n,
- input PPS_IN,
- output reset_codec,
-
// GPIF
- inout [15:0] GPIF_D,
- input [3:0] GPIF_CTL,
- output [3:0] GPIF_RDY,
- input FX2_PA7_FLAGD,
- input FX2_PA6_PKTEND,
- input FX2_PA2_SLOE,
+ inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
+ input FX2_PA7_FLAGD, input FX2_PA6_PKTEND, input FX2_PA2_SLOE,
input IFCLK,
- output [2:0] debug_led,
+ inout SDA_FPGA, inout SCL_FPGA, // I2C
- // Debug bus
- output [1:0] debug_clk,
- output [31:0] debug,
-
- input [11:0] adc,
- input RXSYNC,
-
- output TXBLANK,
- output TXSYNC,
- output [13:0] dac,
+ output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI
+ output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI
+ output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI
- // TX DB
- inout [15:0] io_tx,
- inout [15:0] io_rx,
+ input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+
+ inout [15:0] io_tx, inout [15:0] io_rx,
- // SPI
- output SEN_AUX, output SCLK_AUX, input MISO_AUX,
- output SEN_CODEC, output SCLK_CODEC, output MOSI_CODEC, input MISO_CODEC,
- output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
- output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB
+ output [13:0] dac, output TXSYNC, output TXBLANK,
+ input [11:0] adc, input RXSYNC,
+
+ input PPS_IN
);
- wire clk_fpga, sys_clk, wb_clk, dcm_out, clk_div, dcm_locked;
+ // /////////////////////////////////////////////////////////////////////////
+ // Clocking
+ wire clk_fpga, clk_fpga_in, reset;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
- defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+ reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset));
- DCM DCM_INST (.CLKFB(sys_clk),
- .CLKIN(clk_fpga),
- .DSSEN(0),
- .PSCLK(0),
- .PSEN(0),
- .PSINCDEC(0),
- .RST(dcm_rst),
- .CLKDV(clk_div),
- .CLKFX(),
- .CLKFX180(),
- .CLK0(dcm_out),
- .CLK2X(),
- .CLK2X180(),
- .CLK90(),
- .CLK180(),
- .CLK270(),
- .LOCKED(dcm_locked),
- .PSDONE(),
- .STATUS());
- defparam DCM_INST.CLK_FEEDBACK = "1X";
- defparam DCM_INST.CLKDV_DIVIDE = 2.0;
- defparam DCM_INST.CLKFX_DIVIDE = 1;
- defparam DCM_INST.CLKFX_MULTIPLY = 4;
- defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
- defparam DCM_INST.CLKIN_PERIOD = 15.625;
- defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
- defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
- defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
- defparam DCM_INST.FACTORY_JF = 16'h8080;
- defparam DCM_INST.PHASE_SHIFT = 0;
- defparam DCM_INST.STARTUP_WAIT = "FALSE";
+ // /////////////////////////////////////////////////////////////////////////
+ // SPI
+ wire mosi, sclk, miso;
+ assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
+ assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
+ assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
+ assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
+ (~SEN_CODEC & MISO_CODEC);
+
+ // /////////////////////////////////////////////////////////////////////////
+ // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+ assign TXBLANK = 0;
+ wire [13:0] tx_i, tx_q;
- BUFG sysclk_BUFG (.I(dcm_out), .O(sys_clk));
- BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+ genvar i;
+ generate
+ for(i=0;i<14;i=i+1)
+ begin : gen_dacout
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(tx_i[i]), // 1-bit data input (associated with C0)
+ .D1(tx_q[i]), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+ end // block: gen_dacout
+ endgenerate
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(1'b0), // 1-bit data input (associated with C0)
+ .D1(1'b1), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
- IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
- IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+ // /////////////////////////////////////////////////////////////////////////
+ // RX ADC -- handles deinterleaving
- wire mosi, miso, sclk;
- assign SCLK_AUX = ~SEN_AUX ? sclk : 2'b00;
- assign {SCLK_CODEC,MOSI_CODEC} = ~SEN_CODEC ? {sclk,mosi} : 2'b00;
- assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'b00;
- assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'b00;
- assign miso = (~SEN_CODEC & MISO_CODEC) | (~SEN_AUX & MISO_AUX) |
- (~SEN_RX_DB & MISO_RX_DB) |(~SEN_TX_DB & MISO_TX_DB);
+ reg [11:0] rx_i, rx_q;
+ wire [11:0] rx_a, rx_b;
- u1_core u1_core
- (.sys_clk(sys_clk), .sys_rst(sys_rst),
- .wb_clk(wb_clk), .wb_rst(wb_rst),
- .uart_tx_o(FPGA_TXD), .uart_rx_i(FPGA_RXD), .uart_baud_o(),
-
- .leds(debug_led), .debug(debug), .debug_clk(debug_clk),
-
- .scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_pad_oen_o(scl_pad_oen_o),
- .sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_pad_oen_o(sda_pad_oen_o),
-
- .pps(PPS_IN),
- .reset_codec(reset_codec),
-
- // GPIF
- .gpif_clk(IFCLK), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
- .gpif_misc({FX2_PA7_FLAGD, FX2_PA6_PKTEND, FX2_PA2_SLOE}),
-
- .adc(adc), .rxsync(RXSYNC),
-
- .txblank(TXBLANK), .txsync(TXSYNC), .dac(dac),
-
- .io_tx(io_tx), .io_rx(io_rx),
-
- // SPI
- .sclk(sclk), .mosi(mosi), .miso(miso), .sen({SEN_AUX, SEN_CODEC, SEN_RX_DB, SEN_TX_DB}),
- .sim_mode(0)
- );
+ genvar j;
+ generate
+ for(j=0;j<12;j=j+1)
+ begin : gen_adcin
+ IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
+ .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock
+ .Q1(rx_b[j]), // 1-bit output captured with C1 clock
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D(adc[j]), // 1-bit DDR data input
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+ end // block: gen_adcin
+ endgenerate
+
+ IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
+ .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock
+ .Q1(rxsync_1), // 1-bit output captured with C1 clock
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D(RXSYNC), // 1-bit DDR data input
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
-endmodule // u1plus
+ always @(posedge clk_fpga)
+ if(rxsync_0)
+ begin
+ rx_i <= rx_a;
+ rx_q <= rx_b;
+ end
+ else
+ begin
+ rx_i <= rx_b;
+ rx_q <= rx_a;
+ end
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Main U1E Core
+ u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+ .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
+ .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}),
+ .gpif_clk(IFCLK),
+ .db_sda(db_sda), .db_scl(db_scl),
+ .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
+ .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon),
+ .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+ .io_tx(io_tx), .io_rx(io_rx),
+ .tx_i(tx_i), .tx_q(tx_q),
+ .rx_i(rx_i), .rx_q(rx_q),
+ .pps_in(PPS_IN) );
+endmodule // u1plus
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 04:44:23 +0000