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-rw-r--r--usrp2/top/u1e/u1e.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 9536b5ced..7ddbfd537 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -5,8 +5,8 @@
module u1e
(input CLK_FPGA_P, input CLK_FPGA_N, // Diff
- output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
- input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD,
+ output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ input debug_pb, output FPGA_TXD, input FPGA_RXD,
// GPMC
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -137,9 +137,9 @@ module u1e
// /////////////////////////////////////////////////////////////////////////
// Main U1E Core
- u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]),
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
.debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
- .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+ .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
.EM_NWE(EM_NWE), .EM_NOE(EM_NOE),