diff options
Diffstat (limited to 'usrp2/top/USRP2')
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 57 |
1 files changed, 9 insertions, 48 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index eae16bfeb..28df79244 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -136,7 +136,7 @@ module u2_core // External RAM input [17:0] RAM_D_pi, - output [17:0] RAM_D_po, + output [17:0] RAM_D_po, output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, @@ -236,13 +236,13 @@ module u2_core .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K) .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // Unused .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // SD Card access + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // Unused .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused .dw(dw),.aw(aw),.sw(sw)) wb_1master @@ -281,7 +281,11 @@ module u2_core .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - + + // Unused Slaves 9 and b-f + assign s9_ack = 0; assign sb_ack = 0; assign sc_ack = 0; + assign sd_ack = 0; assign se_ack = 0; assign fc_ack = 0; + // //////////////////////////////////////////////////////////////////////////////////////// // Reset Controller system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), @@ -531,20 +535,6 @@ module u2_core .irq(irq) ); // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - /* - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - */ - // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries @@ -553,36 +543,7 @@ module u2_core .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - /* - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - */ - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - /* - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - */ // ///////////////////////////////////////////////////////////////////////// // ADC Frontend wire [23:0] adc_i, adc_q; |