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-rw-r--r--usrp2/top/USRP2/u2_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index a631ae9b1..120b8c888 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -421,11 +421,11 @@ module u2_core
wire [31:0] spi_debug;
wire [31:0] spi_readback;
wire spi_ready;
- simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(9)) shared_spi(
+ simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(8)) shared_spi(
.clock(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.readback(spi_readback), .ready(spi_ready),
- .sen({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sen({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
.sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
);