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-rw-r--r--usrp2/top/USRP2/Makefile10
1 files changed, 7 insertions, 3 deletions
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile
index adfaf06c4..1fc375c76 100644
--- a/usrp2/top/USRP2/Makefile
+++ b/usrp2/top/USRP2/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2_rev3
BUILD_DIR = $(abspath build)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"