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-rw-r--r--usrp2/top/N2x0/Makefile.N210R42
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 315388586..44ce17b3f 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
-"Verilog Macros" "LVDS=1 FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)"
+"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"