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-rw-r--r--usrp2/top/N2x0/Makefile.N210R44
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 73747e544..01a9e19fd 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -45,7 +45,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \
# Sources
##################################################
TOP_SRCS = \
-rev4_defs.v \
capture_ddrlvds.v \
u2plus_core.v \
u2plus.v \
@@ -67,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "LVDS=1"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"