5 files changed, 9 insertions, 9 deletions
diff --git a/usrp2/top/E1x0/E100.ucf b/usrp2/top/E1x0/E1x0.ucf
index 278fc289a..278fc289a 100644
--- a/usrp2/top/E1x0/E100.ucf
+++ b/usrp2/top/E1x0/E1x0.ucf
diff --git a/usrp2/top/E1x0/E100.v b/usrp2/top/E1x0/E1x0.v
index 080ae24c7..e7b0a4e00 100644
--- a/usrp2/top/E1x0/E100.v
+++ b/usrp2/top/E1x0/E1x0.v
@@ -18,7 +18,7 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
-module E100
+module E1x0
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input debug_pb, output FPGA_TXD, input FPGA_RXD,
@@ -193,4 +193,4 @@ module E100
     //assign debug = gpmc_debug;
     assign debug = core_debug;
 
-endmodule // E100
+endmodule // E1x0
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 2b0ae8367..92334d987 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = E100
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E100)
 
 # set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 TOP_SRCS = \
 ../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 8de0714c3..e5be8d2fa 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
 # set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 TOP_SRCS = \
 ../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf
index 16f06dab7..6bd559426 100644
--- a/usrp2/top/E1x0/timing.ucf
+++ b/usrp2/top/E1x0/timing.ucf
@@ -14,7 +14,7 @@ INST "EM_NCS6" TNM = gpmc_net;
 INST "EM_NWE" TNM = gpmc_net;
 INST "EM_NOE" TNM = gpmc_net;
 
-TIMEGRP "gpmc_net" OFFSET = IN 5 ns VALID 10 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net" OFFSET = IN 7 ns VALID 14 ns BEFORE "EM_CLK" FALLING;
 TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
 
 #constrain interrupt lines