diff options
Diffstat (limited to 'usrp2/top/E1x0')
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 2 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 7 |
2 files changed, 5 insertions, 4 deletions
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile index 02d7f006e..14e138fa3 100755 --- a/usrp2/top/E1x0/core_compile +++ b/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 9257e5541..bd7bd26f6 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -233,8 +233,9 @@ module u1e_core .debug(debug_vt)); duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug() ); @@ -445,7 +446,7 @@ module u1e_core .strobe(set_stb),.addr(set_addr),.data(set_data) ); user_settings #(.BASE(SR_USER_REGS)) user_settings - (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb), + (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb), .set_addr(set_addr),.set_data(set_data), .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) ); |