3 files changed, 15 insertions, 7 deletions
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 397bac618..ad5a0c1bd 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -8,6 +8,10 @@
 TOP_MODULE = u1e
 BUILD_DIR = $(abspath build$(ISE)-E100)
 
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
 ##################################################
 # Include other makefiles
 ##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpmc/Makefile.srcs
-include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
 "Register Balancing" Yes \
 "Use Clock Enable" Auto \
 "Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
 
 TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 1f95954ae..291ac0a44 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -8,6 +8,10 @@
 TOP_MODULE = u1e
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
 ##################################################
 # Include other makefiles
 ##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpmc/Makefile.srcs
-include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
 "Register Balancing" Yes \
 "Use Clock Enable" Auto \
 "Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
 
 TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 5f2edca1a..765023e29 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -220,7 +220,7 @@ module u1e_core
    wire [31:0]   sample_tx;
    wire strobe_tx;
 
-   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
+   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
 		   .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
 		   .DSP_NUMBER(0))