diff options
Diffstat (limited to 'usrp2/top/E1x0')
| -rw-r--r-- | usrp2/top/E1x0/u1e.v | 31 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 8 |
2 files changed, 22 insertions, 17 deletions
diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v index adf42fd07..1ec214e76 100644 --- a/usrp2/top/E1x0/u1e.v +++ b/usrp2/top/E1x0/u1e.v @@ -36,11 +36,12 @@ module u1e output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + output overo_gpio144, output overo_gpio146, // Fifo controls input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO - input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO - input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO + input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO inout [15:0] io_tx, inout [15:0] io_rx, @@ -78,16 +79,25 @@ module u1e .CLK2X(), .CLK2X180(), .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); - + // ///////////////////////////////////////////////////////////////////////// // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; - assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | - (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + //assign the aux spi to the cgen (bypasses wishbone) + assign cgen_sclk = overo_gpio65; + assign cgen_sen_b = overo_gpio128; + assign cgen_mosi = overo_gpio145; + assign overo_gpio147 = cgen_miso; + + wire _cgen_sen_b; + //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi // ///////////////////////////////////////////////////////////////////////// // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL @@ -137,17 +147,14 @@ module u1e .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), - .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .sclk(sclk), .sen({_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), - .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .tx_have_space(overo_gpio144), + .rx_have_data(overo_gpio146), .io_tx(io_tx), .io_rx(io_rx), .tx_i(tx_i), .tx_q(tx_q), .rx_i(DA), .rx_q(DB), - .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, - {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, - {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); // ///////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 4c513587b..02dfd6177 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -31,12 +31,12 @@ module u1e_core output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + output tx_have_space, output rx_have_data, inout [15:0] io_tx, inout [15:0] io_rx, output [13:0] tx_i, output [13:0] tx_q, input [11:0] rx_i, input [11:0] rx_q, - input [11:0] misc_gpio, input pps_in + input pps_in ); localparam TXFIFOSIZE = 13; @@ -70,9 +70,7 @@ module u1e_core wire [31:0] debug_vt; wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; - + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(global_reset)); |