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-rw-r--r--usrp2/top/E1x0/Makefile.passthru98
-rw-r--r--usrp2/top/E1x0/passthru.ucf6
-rw-r--r--usrp2/top/E1x0/passthru.v35
-rw-r--r--usrp2/top/E1x0/u1e.v31
-rw-r--r--usrp2/top/E1x0/u1e_core.v10
5 files changed, 24 insertions, 156 deletions
diff --git a/usrp2/top/E1x0/Makefile.passthru b/usrp2/top/E1x0/Makefile.passthru
deleted file mode 100644
index f2d835608..000000000
--- a/usrp2/top/E1x0/Makefile.passthru
+++ /dev/null
@@ -1,98 +0,0 @@
-#
-# Copyright 2008 Ettus Research LLC
-#
-
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE = passthru
-BUILD_DIR = $(abspath build$(ISE))
-
-##################################################
-# Include other makefiles
-##################################################
-
-include ../Makefile.common
-include ../../fifo/Makefile.srcs
-include ../../control_lib/Makefile.srcs
-include ../../sdr_lib/Makefile.srcs
-include ../../serdes/Makefile.srcs
-include ../../simple_gemac/Makefile.srcs
-include ../../timing/Makefile.srcs
-include ../../opencores/Makefile.srcs
-include ../../vrt/Makefile.srcs
-include ../../udp/Makefile.srcs
-include ../../coregen/Makefile.srcs
-include ../../gpmc/Makefile.srcs
-
-##################################################
-# Project Properties
-##################################################
-export PROJECT_PROPERTIES := \
-family "Spartan-3A DSP" \
-device xc3sd1800a \
-package cs484 \
-speed -4 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE
-
-##################################################
-# Sources
-##################################################
-TOP_SRCS = \
-passthru.v \
-passthru.ucf
-
-SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
-$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \
-$(GPMC_SRCS)
-
-##################################################
-# Process Properties
-##################################################
-SYNTHESIZE_PROPERTIES = \
-"Number of Clock Buffers" 8 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
-
-TRANSLATE_PROPERTIES = \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-MAP_PROPERTIES = \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-PLACE_ROUTE_PROPERTIES = \
-"Place & Route Effort Level (Overall)" High
-
-STATIC_TIMING_PROPERTIES = \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-GEN_PROG_FILE_PROPERTIES = \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/E1x0/passthru.ucf b/usrp2/top/E1x0/passthru.ucf
deleted file mode 100644
index 64e6f0440..000000000
--- a/usrp2/top/E1x0/passthru.ucf
+++ /dev/null
@@ -1,6 +0,0 @@
-NET "overo_gpio145" LOC = "C7" ;
-NET "cgen_mosi" LOC = "E22" ;
-NET "cgen_sclk" LOC = "J19" ;
-NET "cgen_sen_b" LOC = "H20" ;
-NET "fpga_cfg_din" LOC = "W17" ;
-NET "fpga_cfg_cclk" LOC = "V17" ;
diff --git a/usrp2/top/E1x0/passthru.v b/usrp2/top/E1x0/passthru.v
deleted file mode 100644
index 486257366..000000000
--- a/usrp2/top/E1x0/passthru.v
+++ /dev/null
@@ -1,35 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module passthru
- (input overo_gpio145,
- output cgen_sclk,
- output cgen_sen_b,
- output cgen_mosi,
- input fpga_cfg_din,
- input fpga_cfg_cclk
- );
-
- assign cgen_sclk = fpga_cfg_cclk;
- assign cgen_sen_b = overo_gpio145;
- assign cgen_mosi = fpga_cfg_din;
-
-
-endmodule // passthru
diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v
index adf42fd07..1ec214e76 100644
--- a/usrp2/top/E1x0/u1e.v
+++ b/usrp2/top/E1x0/u1e.v
@@ -36,11 +36,12 @@ module u1e
output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI
input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+ input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI
- output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls
+ output overo_gpio144, output overo_gpio146, // Fifo controls
input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO
- input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO
- input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO
+ input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO
+ input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO
inout [15:0] io_tx, inout [15:0] io_rx,
@@ -78,16 +79,25 @@ module u1e
.CLK2X(), .CLK2X180(),
.CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(),
.LOCKED(dcm_locked), .STATUS());
-
+
// /////////////////////////////////////////////////////////////////////////
// SPI
wire mosi, sclk, miso;
assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
- assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0;
+ //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi
assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
- (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+ (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+
+ //assign the aux spi to the cgen (bypasses wishbone)
+ assign cgen_sclk = overo_gpio65;
+ assign cgen_sen_b = overo_gpio128;
+ assign cgen_mosi = overo_gpio145;
+ assign overo_gpio147 = cgen_miso;
+
+ wire _cgen_sen_b;
+ //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi
// /////////////////////////////////////////////////////////////////////////
// TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
@@ -137,17 +147,14 @@ module u1e
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5),
.EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
.db_sda(db_sda), .db_scl(db_scl),
- .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
+ .sclk(sclk), .sen({_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
.cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon),
.cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
- .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
- .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+ .tx_have_space(overo_gpio144),
+ .rx_have_data(overo_gpio146),
.io_tx(io_tx), .io_rx(io_rx),
.tx_i(tx_i), .tx_q(tx_q),
.rx_i(DA), .rx_q(DB),
- .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176},
- {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22},
- {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}),
.pps_in(PPS_IN) );
// /////////////////////////////////////////////////////////////////////////
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 2c9fc346e..dff712a2f 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -31,12 +31,12 @@ module u1e_core
output sclk, output [15:0] sen, output mosi, input miso,
input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
- output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+ output tx_have_space, output rx_have_data,
inout [15:0] io_tx, inout [15:0] io_rx,
output [13:0] tx_i, output [13:0] tx_q,
input [11:0] rx_i, input [11:0] rx_q,
- input [11:0] misc_gpio, input pps_in
+ input pps_in
);
localparam TXFIFOSIZE = 13;
@@ -59,8 +59,7 @@ module u1e_core
localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
localparam SR_GLOBAL_RESET = 63; // 1 reg
-
- wire [7:0] COMPAT_NUM = 8'd4;
+ wire [7:0] COMPAT_NUM = 8'd5;
wire wb_clk = clk_fpga;
wire wb_rst, global_reset;
@@ -441,8 +440,9 @@ module u1e_core
wire [31:0] reg_test32;
+ //this setting reg is persistent across resets, to check for fpga loaded
setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32
- (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ (.clk(wb_clk),.rst(/*wb_rst*/1'b0),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(reg_test32),.changed());
wb_readback_mux_16LE readback_mux_32
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 14:49:41 +0000