diff options
Diffstat (limited to 'usrp2/top/E1x0')
| -rw-r--r-- | usrp2/top/E1x0/.gitignore | 6 | ||||
| -rw-r--r-- | usrp2/top/E1x0/Makefile | 101 | ||||
| -rw-r--r-- | usrp2/top/E1x0/README | 4 | ||||
| -rw-r--r-- | usrp2/top/E1x0/cmdfile | 20 | ||||
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 3 | ||||
| -rw-r--r-- | usrp2/top/E1x0/make.sim | 7 | ||||
| -rw-r--r-- | usrp2/top/E1x0/tb_u1e.v | 58 | ||||
| -rw-r--r-- | usrp2/top/E1x0/timing.ucf | 13 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e.ucf | 259 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e.v | 166 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 524 |
11 files changed, 0 insertions, 1161 deletions
diff --git a/usrp2/top/E1x0/.gitignore b/usrp2/top/E1x0/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/usrp2/top/E1x0/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/usrp2/top/E1x0/Makefile b/usrp2/top/E1x0/Makefile deleted file mode 100644 index 19fb93ebf..000000000 --- a/usrp2/top/E1x0/Makefile +++ /dev/null @@ -1,101 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u1e_core.v \ -u1e.v \ -u1e.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Generate Detailed MAP Report" TRUE \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/E1x0/README b/usrp2/top/E1x0/README deleted file mode 100644 index 14c7a4955..000000000 --- a/usrp2/top/E1x0/README +++ /dev/null @@ -1,4 +0,0 @@ - -make clean -make sim -./tb_u1e -lxt2 diff --git a/usrp2/top/E1x0/cmdfile b/usrp2/top/E1x0/cmdfile deleted file mode 100644 index 291c723b8..000000000 --- a/usrp2/top/E1x0/cmdfile +++ /dev/null @@ -1,20 +0,0 @@ - -# My stuff --y . --y ../../control_lib --y ../../control_lib/newfifo --y ../../sdr_lib --y ../../timing --y ../../coregen --y ../../gpmc - -# Models --y ../../models --y /opt/Xilinx/10.1/ISE/verilog/src/unisims - -# Open Cores --y ../../opencores/spi/rtl/verilog -+incdir+../../opencores/spi/rtl/verilog --y ../../opencores/i2c/rtl/verilog -+incdir+../../opencores/i2c/rtl/verilog - diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile deleted file mode 100755 index 02d7f006e..000000000 --- a/usrp2/top/E1x0/core_compile +++ /dev/null @@ -1,3 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models - - diff --git a/usrp2/top/E1x0/make.sim b/usrp2/top/E1x0/make.sim deleted file mode 100644 index 1c163884c..000000000 --- a/usrp2/top/E1x0/make.sim +++ /dev/null @@ -1,7 +0,0 @@ -all: sim - -sim: - iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e - -clean: - rm -f tb_u1e *.vcd *.lxt a.out diff --git a/usrp2/top/E1x0/tb_u1e.v b/usrp2/top/E1x0/tb_u1e.v deleted file mode 100644 index 188190f04..000000000 --- a/usrp2/top/E1x0/tb_u1e.v +++ /dev/null @@ -1,58 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -`timescale 1ps / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module tb_u1e(); - - wire [2:0] debug_led; - wire [31:0] debug; - wire [1:0] debug_clk; - - xlnx_glbl glbl (.GSR(),.GTS()); - - initial begin - $dumpfile("tb_u1e.lxt"); - $dumpvars(0,tb_u1e); - end - - // GPMC - wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; - wire [15:0] EM_D; - wire [10:1] EM_A; - wire [1:0] EM_NBE; - - reg clk_fpga = 0, rst_fpga = 1; - always #15625 clk_fpga = ~clk_fpga; - - initial #200000 - @(posedge clk_fpga) - rst_fpga <= 0; - - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - - gpmc_model_async gpmc_model_async - (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // tb_u1e diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf deleted file mode 100644 index 8df28c9d3..000000000 --- a/usrp2/top/E1x0/timing.ucf +++ /dev/null @@ -1,13 +0,0 @@ - -NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; - - - - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/top/E1x0/u1e.ucf b/usrp2/top/E1x0/u1e.ucf deleted file mode 100644 index 0c487a601..000000000 --- a/usrp2/top/E1x0/u1e.ucf +++ /dev/null @@ -1,259 +0,0 @@ - -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -NET "EM_NBE<1>" LOC = "D14" ; -NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -#NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; - -## Overo GPIO -NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug -NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug -NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug -NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug -NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug -NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug -NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug - -NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 -NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 - -NET "overo_gpio144" LOC = "A5" ; # tx_have_space -NET "overo_gpio145" LOC = "C7" ; # tx_underrun -NET "overo_gpio146" LOC = "A6" ; # rx_have_data -NET "overo_gpio147" LOC = "B6" ; # rx_overrun -NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug -NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug -NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug - -## Overo UART -#NET "overo_txd1" LOC = "C6" ; -#NET "overo_rxd1" LOC = "D6" ; - -## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "G19" ; -NET "FPGA_RXD" LOC = "F20" ; - -#NET "SYSEN" LOC = "C11" ; - -## I2C -NET "db_scl" LOC = "F19" ; -NET "db_sda" LOC = "F18" ; - -## SPI -### DBoard SPI -NET "db_sclk_rx" LOC = "D21" ; -NET "db_miso_rx" LOC = "D22" ; -NET "db_mosi_rx" LOC = "D20" ; -NET "db_sen_rx" LOC = "E19" ; -NET "db_sclk_tx" LOC = "F21" ; -NET "db_miso_tx" LOC = "E20" ; -NET "db_mosi_tx" LOC = "G17" ; -NET "db_sen_tx" LOC = "G18" ; - -### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "G3" ; -#NET "aux_sdo_codec" LOC = "F3" ; -#NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; -NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; -NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; - -### Clock Gen SPI -NET "cgen_miso" LOC = "F22" ; -NET "cgen_mosi" LOC = "E22" ; -NET "cgen_sclk" LOC = "J19" ; -NET "cgen_sen_b" LOC = "H20" ; - -## Clock gen control -NET "cgen_st_status" LOC = "P20" ; -NET "cgen_st_ld" LOC = "R17" ; -NET "cgen_st_refmon" LOC = "P17" ; -NET "cgen_sync_b" LOC = "U18" ; -NET "cgen_ref_sel" LOC = "U19" ; - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; - -#NET "reset_codec" LOC = "C2" ; - -NET "RXSYNC" LOC = "F2" ; -NET "DB<11>" LOC = "G6" ; -NET "DB<10>" LOC = "G5" ; -NET "DB<9>" LOC = "E4" ; -NET "DB<8>" LOC = "E3" ; -NET "DB<7>" LOC = "H6" ; -NET "DB<6>" LOC = "H5" ; -NET "DB<5>" LOC = "H1" ; -NET "DB<4>" LOC = "G1" ; -NET "DB<3>" LOC = "K5" ; -NET "DB<2>" LOC = "K4" ; -NET "DB<1>" LOC = "H2" ; -NET "DB<0>" LOC = "L5" ; - -NET "DA<11>" LOC = "K6" ; -NET "DA<10>" LOC = "K3" ; -NET "DA<9>" LOC = "K2" ; -NET "DA<8>" LOC = "N1" ; -NET "DA<7>" LOC = "N5" ; -NET "DA<6>" LOC = "N6" ; -NET "DA<5>" LOC = "P2" ; -NET "DA<4>" LOC = "P1" ; -NET "DA<3>" LOC = "R6" ; -NET "DA<2>" LOC = "P6" ; -NET "DA<1>" LOC = "R1" ; -NET "DA<0>" LOC = "R2" ; - -NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; - -NET "PPS_IN" LOC = "M5" ; - -NET "io_tx<0>" LOC = "AB20" ; -NET "io_tx<1>" LOC = "Y17" ; -NET "io_tx<2>" LOC = "Y16" ; -NET "io_tx<3>" LOC = "U16" ; -NET "io_tx<4>" LOC = "V16" ; -NET "io_tx<5>" LOC = "AB19" ; -NET "io_tx<6>" LOC = "AA19" ; -NET "io_tx<7>" LOC = "U14" ; -NET "io_tx<8>" LOC = "U15" ; -NET "io_tx<9>" LOC = "AB17" ; -NET "io_tx<10>" LOC = "AB18" ; -NET "io_tx<11>" LOC = "Y13" ; -NET "io_tx<12>" LOC = "W14" ; -NET "io_tx<13>" LOC = "U13" ; -NET "io_tx<14>" LOC = "AA15" ; -NET "io_tx<15>" LOC = "AB14" ; - -NET "io_rx<0>" LOC = "Y8" ; -NET "io_rx<1>" LOC = "Y9" ; -NET "io_rx<2>" LOC = "V7" ; -NET "io_rx<3>" LOC = "U8" ; -NET "io_rx<4>" LOC = "V10" ; -NET "io_rx<5>" LOC = "U9" ; -NET "io_rx<6>" LOC = "AB7" ; -NET "io_rx<7>" LOC = "AA8" ; -NET "io_rx<8>" LOC = "W8" ; -NET "io_rx<9>" LOC = "V8" ; -NET "io_rx<10>" LOC = "AB5" ; -NET "io_rx<11>" LOC = "AB6" ; -NET "io_rx<12>" LOC = "AB4" ; -NET "io_rx<13>" LOC = "AA4" ; -NET "io_rx<14>" LOC = "W5" ; -NET "io_rx<15>" LOC = "Y4" ; - -#NET "CLKOUT2_CODEC" LOC = "U12" ; -#NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unused -#NET "unnamed_net53" LOC = "B1" ; # TMS -#NET "unnamed_net52" LOC = "B22" ; # TDO -#NET "unnamed_net51" LOC = "D2" ; # TDI -#NET "unnamed_net50" LOC = "A21" ; # TCK -#NET "unnamed_net59" LOC = "F7" ; # PUDC_B -#NET "unnamed_net58" LOC = "V6" ; # M2 -#NET "unnamed_net57" LOC = "AA3" ; # M1 -#NET "unnamed_net56" LOC = "AB3" ; # M0 -#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v deleted file mode 100644 index dbd6173f3..000000000 --- a/usrp2/top/E1x0/u1e.v +++ /dev/null @@ -1,166 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u1e - (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, output FPGA_TXD, input FPGA_RXD, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, - input EM_NWE, input EM_NOE, - - inout db_sda, inout db_scl, // I2C - - output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI - output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI - output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI - output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI - - output overo_gpio144, output overo_gpio146, // Fifo controls - input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO - input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO - input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO - - inout [15:0] io_tx, inout [15:0] io_rx, - - output [13:0] TX, output TXSYNC, output TXBLANK, - input [11:0] DA, input [11:0] DB, input RXSYNC, - - input PPS_IN - ); - - // ///////////////////////////////////////////////////////////////////////// - // Clocking - wire clk_fpga, clk_fpga_in; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - wire clk_2x, dcm_rst, dcm_locked, clk_fb; - DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2 ), - .CLKFX_DIVIDE ( 2 ), - .CLKFX_MULTIPLY ( 2 ), - .CLKIN_DIVIDE_BY_2 ( "FALSE" ), - .CLKIN_PERIOD ( 15.625 ), - .CLKOUT_PHASE_SHIFT ( "NONE" ), - .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), - .DFS_FREQUENCY_MODE ( "LOW" ), - .DLL_FREQUENCY_MODE ( "LOW" ), - .DUTY_CYCLE_CORRECTION ( "TRUE" ), - .FACTORY_JF ( 16'h8080 ), - .PHASE_SHIFT ( 0 ), - .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), - .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), - .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(), .CLK2X180(), - .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), - .LOCKED(dcm_locked), .STATUS()); - - // ///////////////////////////////////////////////////////////////////////// - // SPI - wire mosi, sclk, miso; - assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; - assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; - assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; - //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi - assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | - (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); - - //assign the aux spi to the cgen (bypasses wishbone) - assign cgen_sclk = overo_gpio65; - assign cgen_sen_b = overo_gpio128; - assign cgen_mosi = overo_gpio145; - wire proc_int; //re-purpose gpio for interrupt when we are not using aux spi - assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : proc_int; - - wire _cgen_sen_b; - //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi - - // ///////////////////////////////////////////////////////////////////////// - // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL - - assign TXBLANK = 0; - wire [13:0] tx_i, tx_q; - - reg[13:0] delay_q; - always @(posedge clk_fpga) - delay_q <= tx_q; - - genvar i; - generate - for(i=0;i<14;i=i+1) - begin : gen_dacout - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(delay_q[i]), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_dacout - endgenerate - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(1'b0), // 1-bit data input (associated with C0) - .D1(1'b1), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - // ///////////////////////////////////////////////////////////////////////// - // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), - .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), - .db_sda(db_sda), .db_scl(db_scl), - .sclk(sclk), .sen({_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), - .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), - .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), - .tx_have_space(overo_gpio144), - .rx_have_data(overo_gpio146), - .io_tx(io_tx), .io_rx(io_rx), - .tx_i(tx_i), .tx_q(tx_q), - .rx_i(DA), .rx_q(DB), - .pps_in(PPS_IN), .proc_int(proc_int) ); - - // ///////////////////////////////////////////////////////////////////////// - // Local Debug - // assign debug_clk = {clk_fpga, clk_2x }; - // assign debug = { TXSYNC, TXBLANK, TX }; - -endmodule // u1e diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v deleted file mode 100644 index c4fc16444..000000000 --- a/usrp2/top/E1x0/u1e_core.v +++ /dev/null @@ -1,524 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - - - -module u1e_core - (input clk_fpga, input rst_fpga, - output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - output debug_txd, input debug_rxd, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, - input EM_NWE, input EM_NOE, - - inout db_sda, inout db_scl, - output sclk, output [15:0] sen, output mosi, input miso, - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_have_space, output rx_have_data, - inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] tx_i, output [13:0] tx_q, - input [11:0] rx_i, input [11:0] rx_q, - - input pps_in, output proc_int - ); - - localparam TXFIFOSIZE = 13; - localparam RXFIFOSIZE = 13; - - // 64 total regs in address space - localparam SR_RX_CTRL0 = 0; // 9 regs (+0 to +8) - localparam SR_RX_DSP0 = 10; // 4 regs (+0 to +3) - localparam SR_RX_CTRL1 = 16; // 9 regs (+0 to +8) - localparam SR_RX_DSP1 = 26; // 4 regs (+0 to +3) - localparam SR_ERR_CTRL = 30; // 1 reg - localparam SR_TX_CTRL = 32; // 4 regs (+0 to +3) - localparam SR_TX_DSP = 38; // 3 regs (+0 to +2) - - localparam SR_TIME64 = 42; // 6 regs (+0 to +5) - localparam SR_RX_FRONT = 48; // 5 regs (+0 to +4) - localparam SR_TX_FRONT = 54; // 5 regs (+0 to +4) - - localparam SR_REG_TEST32 = 60; // 1 reg - localparam SR_CLEAR_RX_FIFO = 61; // 1 reg - localparam SR_CLEAR_TX_FIFO = 62; // 1 reg - localparam SR_GLOBAL_RESET = 63; // 1 reg - - wire [7:0] COMPAT_NUM = 8'd5; - - wire wb_clk = clk_fpga; - wire wb_rst, global_reset; - - wire pps_int; - wire [63:0] vita_time, vita_time_pps; - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - wire [7:0] test_rate; - wire [3:0] test_ctrl; - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire [31:0] debug_vt; - wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - wire rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1; - wire tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; - - setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(global_reset)); - - reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // GPMC Slave to Wishbone Master - localparam dw = 16; - localparam aw = 11; - localparam sw = 2; - - wire [dw-1:0] m0_dat_mosi, m0_dat_miso; - wire [aw-1:0] m0_adr; - wire [sw-1:0] m0_sel; - wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - - wire [31:0] debug_gpmc; - - wire [35:0] tx_data, rx_data, tx_err_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, - tx_err_src_rdy, tx_err_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; - - wire bus_error; - wire clear_tx, clear_rx; - - setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_rx)); - - setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpmc (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), - .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), - - .test_rate(test_rate), .test_ctrl(test_ctrl), - .debug(debug_gpmc)); - - wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; - - // ///////////////////////////////////////////////////////////////////////// - // RX ADC Frontend, does IQ Balance, DC Offset, muxing - - wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p - wire run_rx, run_rx0, run_rx1; - - rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,4'b00}),.adc_ovf_a(0), - .adc_b({rx_q,4'b00}),.adc_ovf_b(0), - .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug()); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - - wire [31:0] sample_rx0; - wire strobe_rx0; - wire [35:0] vita_rx_data0; - wire vita_rx_src_rdy0, vita_rx_dst_rdy0; - - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain0 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - - wire [31:0] sample_rx1; - wire strobe_rx1; - wire [35:0] vita_rx_data1; - wire vita_rx_src_rdy1, vita_rx_dst_rdy1; - - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .debug() ); - - vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain1 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // RX Stream muxing - - fifo36_mux #(.prio(0)) mux_data_streams - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0), - .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [23:0] tx_i_int, tx_q_int; - wire run_tx; - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .tx_i(tx_i_int),.tx_q(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), - .debug(debug_vt)); - - tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend - (.clk(wb_clk), .rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), - .dac_a(tx_i), .dac_b(tx_q)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Wishbone Intercon, single master - wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, - s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, - s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, - sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; - wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; - wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; - wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; - wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; - wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; - wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; - - wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), - .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), - .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), - .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), - .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), - .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide - .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), - .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), - .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) - wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - - assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; - assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, Misc LEDs, Switches, controls - - localparam REG_LEDS = 7'd0; // out - localparam REG_CGEN_CTRL = 7'd4; // out - localparam REG_CGEN_ST = 7'd6; // in - localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // in - localparam REG_TX_FRAMELEN = 7'd12; // out - localparam REG_XFER_RATE = 7'd14; // out - localparam REG_COMPAT = 7'd16; // in - - always @(posedge wb_clk) - if(wb_rst) - begin - reg_leds <= 0; - reg_cgen_ctrl <= 2'b11; - reg_test <= 0; - tx_frame_len <= 0; - xfer_rate <= 0; - end - else - if(s0_cyc & s0_stb & s0_we) - case(s0_adr[6:0]) - REG_LEDS : - reg_leds <= s0_dat_mosi; - REG_CGEN_CTRL : - reg_cgen_ctrl <= s0_dat_mosi; - REG_TEST : - reg_test <= s0_dat_mosi; - REG_TX_FRAMELEN : - tx_frame_len <= s0_dat_mosi; - REG_XFER_RATE : - xfer_rate <= s0_dat_mosi; - endcase // case (s0_adr[6:0]) - - assign test_ctrl = xfer_rate[11:8]; - assign test_rate = xfer_rate[7:0]; - - assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; - assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - - assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : - (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : - (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : - (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : - 16'hBEEF; - - assign s0_ack = s0_stb & s0_cyc; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 1, UART - // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), - .rx_int_o(),.tx_int_o(), - .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 2, SPI - - spi_top16 shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), - .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), - .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // Slave 3, I2C - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; - i2c_master_top #(.ARST_LVL(1)) i2c - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_miso[15:8] = 8'd0; - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - - wire [31:0] atr_lines; - wire [31:0] debug_gpio_0, debug_gpio_1; - - nsgpio16LE - nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - //////////////////////////////////////////////////////////////////////////// - // FIFO to WB slave for async messages - Slave #5 - - //signals between fifo and buffer module - wire [35:0] _tx_err_data; - wire _tx_err_src_rdy, _tx_err_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) err_fifo( - .clk(wb_clk), .reset(wb_rst), .clear(wb_rst), - .datain(tx_err_data), .src_rdy_i(tx_err_src_rdy), .dst_rdy_o(tx_err_dst_rdy), - .dataout(_tx_err_data), .src_rdy_o(_tx_err_src_rdy), .dst_rdy_i(_tx_err_dst_rdy) - ); - - wire [31:0] err_status, err_data32; - //the buffer is 32 bits, but the data is 16, so mux based on the addr bit - assign s5_dat_miso = (s5_adr[1] == 1'b0)? err_data32[15:0] : err_data32[31:16]; - - buffer_int2 #(.BASE(SR_ERR_CTRL), .BUF_SIZE(5)) fifo_to_wb( - .clk(wb_clk), .rst(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(err_status), - // Wishbone interface to RAM - .wb_clk_i(wb_clk), .wb_rst_i(wb_rst), - .wb_we_i(s5_we), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_i({16'b0, s5_dat_mosi}), - .wb_dat_o(err_data32), .wb_ack_o(s5_ack), - // Write FIFO Interface - .wr_data_i(_tx_err_data), .wr_ready_i(_tx_err_src_rdy), .wr_ready_o(_tx_err_dst_rdy), - // Read FIFO Interface - .rd_data_o(), .rd_ready_o(), .rd_ready_i(1'b0) - ); - - //////////////////////////////////////////////////////////////////////////// - // Interrupts - - assign proc_int = (|err_status[1:0]); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #8 + 9 - - // only have 64 regs, 32 bits each with current setup... - settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), - .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data) ); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller -- Slave #6 - - atr_controller16 atr_controller16 - (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), - .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); - - // ///////////////////////////////////////////////////////////////////////// - // Readback mux 32 -- Slave #7 - - wire [31:0] reg_test32; - - //this setting reg is persistent across resets, to check for fpga loaded - setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 - (.clk(wb_clk),.rst(/*wb_rst*/1'b0),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(reg_test32),.changed()); - - wb_readback_mux_16LE readback_mux_32 - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), - - .word00(vita_time[63:32]), .word01(vita_time[31:0]), - .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), - .word04(reg_test32), .word05(err_status), - .word06(32'b0), .word07(32'b0), - .word08(32'b0), .word09(32'b0), - .word10(32'b0), .word11(32'b0), - .word12(32'b0), .word13(32'b0), - .word14(32'b0), .word15(32'b0) - ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit - (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(0)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug circuitry - - assign debug_clk = { EM_CLK, clk_fpga }; - -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, - { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, - { EM_D } }; - -*/ - assign debug = debug_gpmc; - - assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx0, tx_i[11:0]}, - {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; - - assign debug_gpio_1 = debug_vt; - -/* - assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, - {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, - {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {2'b0, bus_error, debug_gpmc[4:0] }, - {misc_gpio[7:0]} }; - */ -endmodule // u1e_core |