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-rw-r--r--usrp2/top/E1x0/Makefile.E1106
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 8de0714c3..e5be8d2fa 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -5,7 +5,7 @@
##################################################
# Project Setup
##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
BUILD_DIR = $(abspath build$(ISE)-E110)
# set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
##################################################
TOP_SRCS = \
../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
timing.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \