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-rw-r--r--usrp2/top/E1x0/Makefile.E1106
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 89e51b523..8de0714c3 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \
# Sources
##################################################
TOP_SRCS = \
-u1e_core.v \
-u1e.v \
-u1e.ucf \
+../B100/u1plus_core.v \
+E100.v \
+E100.ucf \
timing.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \