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-rw-r--r--usrp2/top/E1x0/Makefile.E1008
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 3ba7e1031..2b0ae8367 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -5,7 +5,7 @@
##################################################
# Project Setup
##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E100
BUILD_DIR = $(abspath build$(ISE)-E100)
# set me in a custom makefile
@@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \
# Sources
##################################################
TOP_SRCS = \
-u1e_core.v \
-u1e.v \
-u1e.ucf \
+../B100/u1plus_core.v \
+E100.v \
+E100.ucf \
timing.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \