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-rw-r--r--usrp2/top/B100/Makefile.B1003
-rwxr-xr-xusrp2/top/B100/core_compile2
-rw-r--r--usrp2/top/B100/u1plus_core.v59
3 files changed, 42 insertions, 22 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 90dd25942..442b0b579 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -21,6 +21,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpif/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -50,7 +51,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
+$(GPIF_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile
index b2ccc8b49..b62cbaee0 100755
--- a/usrp2/top/B100/core_compile
+++ b/usrp2/top/B100/core_compile
@@ -1 +1 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 0bada703c..1981123bc 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -56,6 +56,7 @@ module u1plus_core
localparam SR_CLEAR_RX_FIFO = 61; // 1 reg
localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
localparam SR_GLOBAL_RESET = 63; // 1 reg
+ localparam SR_USER_REGS = 64; // 2 regs
localparam SR_GPIO = 128; // 5 regs
@@ -65,11 +66,11 @@ module u1plus_core
wire pps_int;
wire [63:0] vita_time, vita_time_pps;
reg [15:0] reg_cgen_ctrl, reg_test;
-
- wire [7:0] set_addr;
- wire [31:0] set_data;
- wire set_stb;
-
+
+ wire [7:0] set_addr, set_addr_user;
+ wire [31:0] set_data, set_data_user;
+ wire set_stb, set_stb_user;
+
wire [31:0] debug0;
wire [31:0] debug1;
@@ -137,20 +138,20 @@ module u1plus_core
.tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
- .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
+ .test_len(0), .test_rate(0), .test_ctrl(0),
.debug0(debug0), .debug1(debug1));
// /////////////////////////////////////////////////////////////////////////
// RX ADC Frontend, does IQ Balance, DC Offset, muxing
- wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p
+ wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a({rx_i,4'b00}),.adc_ovf_a(0),
.adc_b({rx_q,4'b00}),.adc_ovf_b(0),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
@@ -160,15 +161,16 @@ module u1plus_core
wire [35:0] vita_rx_data0;
wire vita_rx_src_rdy0, vita_rx_dst_rdy0;
- dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
@@ -183,15 +185,16 @@ module u1plus_core
wire [35:0] vita_rx_data1;
wire vita_rx_src_rdy1, vita_rx_dst_rdy1;
- dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
@@ -210,10 +213,12 @@ module u1plus_core
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
- wire [23:0] tx_i_int, tx_q_int;
wire run_tx;
-
- vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ wire [23:0] tx_fe_i, tx_fe_q;
+ wire [31:0] sample_tx;
+ wire strobe_tx;
+
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
@@ -223,14 +228,22 @@ module u1plus_core
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
- .tx_i(tx_i_int),.tx_q(tx_q_int),
+ .sample(sample_tx), .strobe(strobe_tx),
.underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+ (.clk(wb_clk),.rst(wb_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug() );
+
tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
(.clk(wb_clk), .rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(tx_i), .dac_b(tx_q));
// /////////////////////////////////////////////////////////////////////////////////////
@@ -392,6 +405,12 @@ module u1plus_core
.wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
.strobe(set_stb),.addr(set_addr),.data(set_data) );
+ user_settings #(.BASE(SR_USER_REGS)) user_settings
+ (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
+ .set_addr(set_addr),.set_data(set_data),
+ .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+ .set_stb_user(set_stb_user) );
+
// /////////////////////////////////////////////////////////////////////////
// Readback mux 32 -- Slave #7
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-12 18:11:38 +0000