diff options
Diffstat (limited to 'usrp2/top/B100')
| -rw-r--r-- | usrp2/top/B100/Makefile.B100 | 15 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 4 |
2 files changed, 13 insertions, 6 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100 index 442b0b579..3cdbb62c0 100644 --- a/usrp2/top/B100/Makefile.B100 +++ b/usrp2/top/B100/Makefile.B100 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -7,7 +7,14 @@ ################################################## TOP_MODULE := B100 BUILD_DIR := build-B100/ -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## include ../Makefile.common include ../../fifo/Makefile.srcs @@ -21,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../gpif/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## # Project Properties @@ -64,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_MOD_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 4c3acaa27..88a8b4f4b 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -37,7 +37,7 @@ module u1plus_core input pps_in ); - localparam TXFIFOSIZE = 12; + localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 12; // 64 total regs in address space @@ -220,7 +220,7 @@ module u1plus_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(0/*no engine*/), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) |