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-rw-r--r--usrp2/timing/time_64bit.v42
-rw-r--r--usrp2/timing/time_receiver.v96
-rw-r--r--usrp2/timing/time_sender.v68
-rw-r--r--usrp2/timing/time_transfer_tb.v26
4 files changed, 162 insertions, 70 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 51c006962..1889e73da 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -3,12 +3,13 @@
module time_64bit
#(parameter TICKS_PER_SEC = 32'd100000000,
parameter BASE = 0)
- (input clk, input rst,
- input set_stb, input [7:0] set_addr, input [31:0] set_data,
- input pps,
- output [63:0] vita_time, output pps_int
- );
-
+ (input clk, input rst,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input pps,
+ output [63:0] vita_time, output pps_int,
+ input exp_time_in, output exp_time_out
+ );
+
localparam NEXT_SECS = 0;
localparam NEXT_TICKS = 1;
localparam PPS_POLSRC = 2;
@@ -91,5 +92,34 @@ module time_64bit
ticks <= ticks_plus_one;
assign pps_int = pps_edge;
+
+ localparam SYNC_RATE = 59999; // Send every 600uS
+ reg [15:0] sync_counter;
+ wire send_sync = (sync_counter == SYNC_RATE);
+ wire sync_rcvd;
+
+ always @(posedge clk)
+ if(rst)
+ sync_counter <= 0;
+ else
+ if(send_sync)
+ sync_counter <= 0;
+ else
+ sync_counter <= sync_counter + 1;
+
+ // must be greater than 1000, 1 less than a multiple of 10;
+
+ time_sender time_sender
+ (.clk(clk),.rst(rst),
+ .vita_time(vita_time),
+ .send_sync(send_sync),
+ .exp_pps_out(exp_pps_out) );
+
+ time_receiver time_receiver
+ (.clk(clk),.rst(rst),
+ .vita_time(vita_time_rcvd),
+ .sync_rcvd(sync_rcvd),
+ .exp_pps_in(exp_pps_in) );
+
endmodule // time_64bit
diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v
index 8e7d3f1ea..71f0ace90 100644
--- a/usrp2/timing/time_receiver.v
+++ b/usrp2/timing/time_receiver.v
@@ -1,9 +1,9 @@
module time_receiver
(input clk, input rst,
- output [31:0] master_time,
+ output reg [63:0] vita_time,
output sync_rcvd,
- input exp_pps_in);
+ input exp_time_in);
wire code_err, disp_err, dispout, complete_word;
reg disp_reg;
@@ -13,7 +13,7 @@ module time_receiver
reg [8:0] dataout_reg;
always @(posedge clk)
- shiftreg <= {exp_pps_in, shiftreg[9:1]};
+ shiftreg <= {exp_time_in, shiftreg[9:1]};
localparam COMMA_0 = 10'h283;
localparam COMMA_1 = 10'h17c;
@@ -55,40 +55,72 @@ module time_receiver
localparam STATE_T1 = 2;
localparam STATE_T2 = 3;
localparam STATE_T3 = 4;
+ localparam STATE_T4 = 5;
+ localparam STATE_T5 = 6;
+ localparam STATE_T6 = 7;
+ localparam STATE_T7 = 8;
+ localparam STATE_TAIL = 9;
localparam HEAD = 9'h13c;
-
- reg [7:0] clock_a, clock_b, clock_c;
- reg [2:0] state;
+ localparam TAIL = 9'h1F7;
+
+ reg [3:0] state;
always @(posedge clk)
if(rst)
state <= STATE_IDLE;
else if(complete_word)
- case(state)
- STATE_IDLE :
- if(dataout_reg == HEAD)
- state <= STATE_T0;
- STATE_T0 :
- begin
- clock_a <= dataout_reg[7:0];
- state <= STATE_T1;
- end
- STATE_T1 :
- begin
- clock_b <= dataout_reg[7:0];
- state <= STATE_T2;
- end
- STATE_T2 :
- begin
- clock_c <= dataout_reg[7:0];
- state <= STATE_T3;
- end
- STATE_T3 :
- state <= STATE_IDLE;
- endcase // case(state)
-
- assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]};
- assign sync_rcvd = (complete_word & (state == STATE_T3));
-
+ if(code_err | disp_err)
+ state <= STATE_IDLE;
+ else
+ case(state)
+ STATE_IDLE :
+ if(dataout_reg == HEAD)
+ state <= STATE_T0;
+ STATE_T0 :
+ begin
+ vita_time[63:56] <= dataout_reg[7:0];
+ state <= STATE_T1;
+ end
+ STATE_T1 :
+ begin
+ vita_time[55:48] <= dataout_reg[7:0];
+ state <= STATE_T2;
+ end
+ STATE_T2 :
+ begin
+ vita_time[47:40] <= dataout_reg[7:0];
+ state <= STATE_T3;
+ end
+ STATE_T3 :
+ begin
+ vita_time[39:32] <= dataout_reg[7:0];
+ state <= STATE_T4;
+ end
+ STATE_T4 :
+ begin
+ vita_time[31:24] <= dataout_reg[7:0];
+ state <= STATE_T5;
+ end
+ STATE_T5 :
+ begin
+ vita_time[23:16] <= dataout_reg[7:0];
+ state <= STATE_T6;
+ end
+ STATE_T6 :
+ begin
+ vita_time[15:8] <= dataout_reg[7:0];
+ state <= STATE_T7;
+ end
+ STATE_T7 :
+ begin
+ vita_time[7:0] <= dataout_reg[7:0];
+ state <= STATE_TAIL;
+ end
+ STATE_TAIL :
+ state <= STATE_IDLE;
+ endcase // case(state)
+
+ assign sync_rcvd = (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+
endmodule // time_sender
diff --git a/usrp2/timing/time_sender.v b/usrp2/timing/time_sender.v
index aa2fcbbdb..f4ee5226a 100644
--- a/usrp2/timing/time_sender.v
+++ b/usrp2/timing/time_sender.v
@@ -2,23 +2,23 @@
module time_sender
(input clk, input rst,
- input [31:0] master_time,
+ input [63:0] vita_time,
input send_sync,
- output exp_pps_out);
+ output reg exp_time_out);
reg [7:0] datain;
reg k;
wire [9:0] dataout;
- reg [9:0] dataout_reg;
- reg disp_reg;
- wire disp, new_word;
+ reg [9:0] dataout_reg;
+ reg disp_reg;
+ wire disp, new_word;
+ reg [4:0] state;
+ reg [3:0] bit_count;
encode_8b10b encode_8b10b
(.datain({k,datain}),.dispin(disp_reg),
.dataout(dataout),.dispout(disp));
- assign exp_pps_out = dataout_reg[0];
-
always @(posedge clk)
if(rst)
disp_reg <= 0;
@@ -33,9 +33,9 @@ module time_sender
else
dataout_reg <= {1'b0,dataout_reg[9:1]};
- reg [4:0] state;
- reg [3:0] bit_count;
-
+ always @(posedge clk)
+ exp_time_out <= dataout_reg[0];
+
assign new_word = (bit_count == 9);
always @(posedge clk)
@@ -52,17 +52,23 @@ module time_sender
localparam SEND_T1 = 3;
localparam SEND_T2 = 4;
localparam SEND_T3 = 5;
+ localparam SEND_T4 = 6;
+ localparam SEND_T5 = 7;
+ localparam SEND_T6 = 8;
+ localparam SEND_T7 = 9;
+ localparam SEND_TAIL = 10;
localparam COMMA = 8'hBC;
localparam HEAD = 8'h3C;
-
- reg [31:0] master_time_reg;
+ localparam TAIL = 8'hF7;
+
+ reg [63:0] vita_time_reg;
always @(posedge clk)
if(rst)
- master_time_reg <= 0;
+ vita_time_reg <= 0;
else if(send_sync)
- master_time_reg <= master_time;
+ vita_time_reg <= vita_time;
always @(posedge clk)
if(rst)
@@ -84,27 +90,51 @@ module time_sender
end
SEND_T0 :
begin
- {k,datain} <= {1'b0, master_time_reg[31:24] };
+ {k,datain} <= {1'b0, vita_time_reg[63:56] };
state <= SEND_T1;
end
SEND_T1 :
begin
- {k,datain} <= {1'b0, master_time_reg[23:16]};
+ {k,datain} <= {1'b0, vita_time_reg[55:48]};
state <= SEND_T2;
end
SEND_T2 :
begin
- {k,datain} <= {1'b0, master_time_reg[15:8]};
+ {k,datain} <= {1'b0, vita_time_reg[47:40]};
state <= SEND_T3;
end
SEND_T3 :
begin
- {k,datain} <= {1'b0, master_time_reg[7:0]};
+ {k,datain} <= {1'b0, vita_time_reg[39:32]};
+ state <= SEND_T4;
+ end
+ SEND_T4 :
+ begin
+ {k,datain} <= {1'b0, vita_time_reg[31:24]};
+ state <= SEND_T5;
+ end
+ SEND_T5 :
+ begin
+ {k,datain} <= {1'b0, vita_time_reg[23:16]};
+ state <= SEND_T6;
+ end
+ SEND_T6 :
+ begin
+ {k,datain} <= {1'b0, vita_time_reg[15:8]};
+ state <= SEND_T7;
+ end
+ SEND_T7 :
+ begin
+ {k,datain} <= {1'b0, vita_time_reg[7:0]};
+ state <= SEND_TAIL;
+ end
+ SEND_TAIL :
+ begin
+ {k,datain} <= {1'b1, TAIL};
state <= SEND_IDLE;
end
default :
state <= SEND_IDLE;
endcase // case(state)
-
endmodule // time_sender
diff --git a/usrp2/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v
index 2b75c60bd..0c164f82c 100644
--- a/usrp2/timing/time_transfer_tb.v
+++ b/usrp2/timing/time_transfer_tb.v
@@ -18,12 +18,12 @@ module time_transfer_tb();
initial #100000000 $finish;
- wire exp_pps, pps, pps_rcv;
- wire [31:0] master_clock_rcv;
- reg [31:0] master_clock = 0;
- reg [31:0] counter = 0;
+ wire exp_time, pps, pps_rcv;
+ wire [63:0] vita_time_rcv;
+ reg [63:0] vita_time = 0;
+ reg [63:0] counter = 0;
- localparam PPS_PERIOD = 109;
+ localparam PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
always @(posedge clk)
if(counter == PPS_PERIOD)
counter <= 0;
@@ -32,19 +32,19 @@ module time_transfer_tb();
assign pps = (counter == (PPS_PERIOD-1));
always @(posedge clk)
- master_clock <= master_clock + 1;
+ vita_time <= vita_time + 1;
time_sender time_sender
(.clk(clk),.rst(rst),
- .master_clock(master_clock),
- .pps(pps),
- .exp_pps_out(exp_pps) );
+ .vita_time(vita_time),
+ .send_sync(pps),
+ .exp_time_out(exp_time) );
time_receiver time_receiver
(.clk(clk),.rst(rst),
- .master_clock(master_clock_rcv),
- .pps(pps_rcv),
- .exp_pps_in(exp_pps) );
+ .vita_time(vita_time_rcv),
+ .sync_rcvd(pps_rcv),
+ .exp_time_in(exp_time) );
- wire [31:0] delta = master_clock - master_clock_rcv;
+ wire [31:0] delta = vita_time - vita_time_rcv;
endmodule // time_transfer_tb
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 22:57:51 +0000