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-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_defines.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index 79509888b..86c301886 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
-`define SPI_DIVIDER_LEN_8
-//`define SPI_DIVIDER_LEN_16
+//`define SPI_DIVIDER_LEN_8
+`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
@@ -66,9 +66,9 @@
// Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
//
-//`define SPI_MAX_CHAR_128
+`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
-`define SPI_MAX_CHAR_32
+//`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8