4 files changed, 80 insertions, 0 deletions
diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs
new file mode 100644
index 000000000..9bcbb29f3
--- /dev/null
+++ b/usrp2/gpif/Makefile.srcs
@@ -0,0 +1,12 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \
+gpif.v \
+gpif_wr.v \
+gpif_rd.v \
+))
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 2da6daa66..9609a5000 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -22,6 +22,21 @@ module gpif
     output [31:0] debug
     );
 
+   wire 	  WR = gpif_ctl[0];
+   wire 	  RD = gpif_ctl[1];
+   wire 	  OE = gpif_ctl[2];
+   
+   gpif_wr gpif_wr
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
+      .gpif_data(), .WR(WR), .have_space(gpif_rdy[0]),
+      .sys_clk(sys_clk), .sys_rst(sys_rst),
+      .data_o(data_o), .src_rdy_o(), .dst_rdy_i(),
+      .debug() );
+   
+
+endmodule // gpif
+
+/*
    wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
    wire [15:0] 	  EM_D_fifo;
    wire [15:0] 	  EM_D_wb;
@@ -120,3 +135,4 @@ module gpif
    assign debug = 0;
    
 endmodule // gpmc_async
+*/
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v
new file mode 100644
index 000000000..f716d4a5d
--- /dev/null
+++ b/usrp2/gpif/gpif_rd.v
@@ -0,0 +1,5 @@
+
+module gpif_rd
+  ();
+   
+endmodule // gpif_rd
diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v
new file mode 100644
index 000000000..c5cdc7597
--- /dev/null
+++ b/usrp2/gpif/gpif_wr.v
@@ -0,0 +1,47 @@
+
+module gpif_wr
+  (input gpif_clk, input gpif_rst,
+   input [15:0] gpif_data, input WR,
+   output reg have_space,
+
+   input sys_clk, input sys_rst,
+   output [19:0] data_o, output src_rdy_o, input dst_rdy_i,
+   output [31:0] debug );
+
+   reg 		 wr_reg;
+   reg [15:0] 	 gpif_data_reg;
+   
+   always @(posedge gpif_clk)
+     begin
+	wr_reg <= WR;
+	gpif_data_reg <= gpif_data;
+     end
+
+   reg [9:0] write_count;
+   
+   always @(posedge gpif_clk)
+     if(gpif_rst)
+       write_count <= 0;
+     else if(wr_reg)
+       write_count <= write_count + 1;
+     else
+       write_count <= 0;
+
+   reg 	     sop;
+   wire      occ = 0;
+   wire      eop = (write_count == 255);
+   
+   always @(posedge gpif_clk)
+     sop <= WR & ~wr_reg;
+
+   wire [15:0] fifo_space;
+   always @(posedge gpif_clk)
+     have_space <= fifo_space > 256;
+   		  
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo
+     (.wclk(gpif_clk), .datain({occ,eop,sop,gpif_data_reg}),
+      .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
+      .rclk(sys_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(),
+      .arst(sys_rst));
+   
+endmodule // gpif_wr