diff options
Diffstat (limited to 'usrp2/gpif/gpif_rd.v')
| -rw-r--r-- | usrp2/gpif/gpif_rd.v | 69 |
1 files changed, 55 insertions, 14 deletions
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index a3167da16..7581592cb 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -1,21 +1,19 @@ module gpif_rd (input gpif_clk, input gpif_rst, - output [15:0] gpif_data, input gpif_rd, output reg have_pkt_rdy, - + output [15:0] gpif_data, input gpif_rd, input gpif_ep, + output reg gpif_empty_d, output reg gpif_empty_c, + input sys_clk, input sys_rst, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + output [31:0] debug ); - wire [15:0] rxfifolevel; - wire [15:0] data_o; + wire [17:0] data_o; wire rx_full; - // USB Read Side of FIFO - always @(negedge gpif_clk) - have_pkt_rdy <= (rxfifolevel >= 256); // FIXME make this more robust - - // 257 Bug Fix + // 33/257 Bug Fix reg [8:0] read_count; always @(negedge gpif_clk) if(gpif_rst) @@ -25,19 +23,62 @@ module gpif_rd else read_count <= 0; + // Data Path wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); - fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo + // FIXME -- handle short packets + wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; + + fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(), .dst_rdy_i(gpif_rd & ~read_count[8]), .occupied(rxfifolevel)); + .dataout(data_o), .src_rdy_o(), .dst_rdy_i(send_data_line), .occupied()); - assign gpif_data = data_o[15:0]; + reg [7:0] packet_count; + always @(negedge gpif_clk) + if(gpif_rst) + packet_count <= 0; + else + if(src_rdy_int & dst_rdy_int & data_int[17]) // eop + if(~(send_data_line & data_o[16])) + packet_count <= packet_count + 1; + else + ; + else + if(send_data_line & data_o[16]) + packet_count <= packet_count - 1; + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_d <= 1; + else + gpif_empty_d <= ~|packet_count; + + // Response Path + wire [15:0] resp_fifolevel; + wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; + wire [17:0] resp_o; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(resp_o), + .src_rdy_o(), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), + .arst(sys_rst)); + + // FIXME -- handle short packets + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_c <= 1; + else + gpif_empty_c <= resp_fifolevel < 16; + + // Output Mux + assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; endmodule // gpif_rd |