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-rw-r--r--usrp2/gpif/gpif.v26
1 files changed, 21 insertions, 5 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index e72490b17..8cac8b466 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -17,7 +17,8 @@ module gpif
input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
+ input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
+
output tx_underrun, output rx_overrun,
input [7:0] test_rate, input [3:0] test_ctrl,
output [31:0] debug0, output [31:0] debug1
@@ -77,8 +78,9 @@ module gpif
wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
wire [18:0] rx19_data;
wire rx19_src_rdy, rx19_dst_rdy;
- wire [18:0] resp_data, resp_int;
- wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int;
+ wire [18:0] resp_data, resp_int1, resp_int2;
+ wire resp_src_rdy, resp_dst_rdy;
+ wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
@@ -106,15 +108,29 @@ module gpif
fifo_to_wb fifo_to_wb
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
- .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
+ .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1),
.wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o),
.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
.triggers(triggers),
.debug0(), .debug1());
+ wire [18:0] tx_err19_data;
+ wire tx_err19_src_rdy, tx_err19_dst_rdy;
+
+ fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o),
+ .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) );
+
+ fifo19_mux #(.prio(0)) mux_err_stream
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1),
+ .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy),
+ .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2));
+
fifo19_pad #(.LENGTH(16)) fifo19_pad
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int),
+ .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2),
.data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
// ////////////////////////////////////////////////////////////////////