diff options
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/fifo/Makefile.srcs | 23 | ||||
| -rw-r--r-- | usrp2/fifo/buffer_int.v | 168 | ||||
| -rw-r--r-- | usrp2/fifo/buffer_int_tb.v | 418 | ||||
| -rw-r--r-- | usrp2/fifo/buffer_pool.v | 283 | ||||
| -rw-r--r-- | usrp2/fifo/buffer_pool_tb.v | 58 | ||||
| -rw-r--r-- | usrp2/fifo/fifo19_to_fifo36.v | 76 | ||||
| -rw-r--r-- | usrp2/fifo/fifo19_to_ll8.v | 53 | ||||
| -rw-r--r-- | usrp2/fifo/fifo36_to_fifo18.v | 40 | ||||
| -rw-r--r-- | usrp2/fifo/fifo36_to_fifo19.v | 41 | ||||
| -rw-r--r-- | usrp2/fifo/fifo36_to_ll8.v | 60 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_2clock.v | 117 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_2clock_cascade.v | 35 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_cascade.v | 52 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_long.v | 148 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_new_tb.vcd | 5506 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_short.v | 95 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_spec.txt | 36 | ||||
| -rw-r--r-- | usrp2/fifo/fifo_tb.v | 158 | ||||
| -rw-r--r-- | usrp2/fifo/ll8_shortfifo.v | 13 | ||||
| -rw-r--r-- | usrp2/fifo/ll8_to_fifo19.v | 73 | ||||
| -rw-r--r-- | usrp2/fifo/ll8_to_fifo36.v | 97 |
22 files changed, 7551 insertions, 0 deletions
diff --git a/usrp2/fifo/.gitignore b/usrp2/fifo/.gitignore new file mode 100644 index 000000000..cba7efc8e --- /dev/null +++ b/usrp2/fifo/.gitignore @@ -0,0 +1 @@ +a.out diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs new file mode 100644 index 000000000..22867da7e --- /dev/null +++ b/usrp2/fifo/Makefile.srcs @@ -0,0 +1,23 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# FIFO Sources +################################################## +FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ +buffer_int.v \ +buffer_pool.v \ +fifo_2clock.v \ +fifo_2clock_cascade.v \ +ll8_shortfifo.v \ +fifo_short.v \ +fifo_long.v \ +fifo_cascade.v \ +fifo36_to_ll8.v \ +ll8_to_fifo36.v \ +fifo19_to_ll8.v \ +ll8_to_fifo19.v \ +fifo36_to_fifo19.v \ +fifo19_to_fifo36.v \ +)) diff --git a/usrp2/fifo/buffer_int.v b/usrp2/fifo/buffer_int.v new file mode 100644 index 000000000..b45ed3532 --- /dev/null +++ b/usrp2/fifo/buffer_int.v @@ -0,0 +1,168 @@ + +// FIFO Interface to the 2K buffer RAMs +// Read port is read-acknowledge +// FIXME do we want to be able to interleave reads and writes? + +module buffer_int + #(parameter BUF_NUM = 0, + parameter BUF_SIZE = 9) + (// Control Interface + input clk, + input rst, + input [31:0] ctrl_word, + input go, + output done, + output error, + output idle, + output [1:0] flag, + + // Buffer Interface + output en_o, + output we_o, + output reg [BUF_SIZE-1:0] addr_o, + output [31:0] dat_to_buf, + input [31:0] dat_from_buf, + + // Write FIFO Interface + input [31:0] wr_data_i, + input [3:0] wr_flags_i, + input wr_ready_i, + output wr_ready_o, + + // Read FIFO Interface + output [31:0] rd_data_o, + output [3:0] rd_flags_o, + output rd_ready_o, + input rd_ready_i + ); + + reg [31:0] ctrl_reg; + reg go_reg; + + always @(posedge clk) + go_reg <= go; + + always @(posedge clk) + if(rst) + ctrl_reg <= 0; + else + if(go & (ctrl_word[31:28] == BUF_NUM)) + ctrl_reg <= ctrl_word; + + wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0]; + wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE]; + + wire read = ctrl_reg[22]; + wire write = ctrl_reg[23]; + wire clear = ctrl_reg[24]; + //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block + //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ? + + localparam IDLE = 3'd0; + localparam PRE_READ = 3'd1; + localparam READING = 3'd2; + localparam WRITING = 3'd3; + localparam ERROR = 3'd4; + localparam DONE = 3'd5; + + reg [2:0] state; + reg rd_sop, rd_eop; + wire wr_sop, wr_eop, wr_error; + reg [1:0] rd_occ; + wire [1:0] wr_occ; + + always @(posedge clk) + if(rst) + begin + state <= IDLE; + rd_sop <= 0; + rd_eop <= 0; + rd_occ <= 0; + end + else + if(clear) + begin + state <= IDLE; + rd_sop <= 0; + rd_eop <= 0; + rd_occ <= 0; + end + else + case(state) + IDLE : + if(go_reg & read) + begin + addr_o <= firstline; + state <= PRE_READ; + end + else if(go_reg & write) + begin + addr_o <= firstline; + state <= WRITING; + end + + PRE_READ : + begin + state <= READING; + addr_o <= addr_o + 1; + rd_occ <= 2'b00; + rd_sop <= 1; + rd_eop <= 0; + end + + READING : + if(rd_ready_i) + begin + rd_sop <= 0; + addr_o <= addr_o + 1; + if(addr_o == lastline) + begin + rd_eop <= 1; + // FIXME assign occ here + rd_occ <= 0; + end + else + rd_eop <= 0; + if(rd_eop) + state <= DONE; + end + + WRITING : + begin + if(wr_ready_i) + begin + addr_o <= addr_o + 1; + if(wr_error) + begin + state <= ERROR; + // Save OCC flags here + end + else if((addr_o == lastline)||wr_eop) + state <= DONE; + end // if (wr_ready_i) + end // case: WRITING + + endcase // case(state) + + assign dat_to_buf = wr_data_i; + assign rd_data_o = dat_from_buf; + + assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop }; + assign rd_ready_o = (state == READING); + + assign wr_sop = wr_flags_i[0]; + assign wr_eop = wr_flags_i[1]; + assign wr_occ = wr_flags_i[3:2]; + assign wr_error = wr_sop & wr_eop; + assign wr_ready_o = (state == WRITING); + + assign we_o = (state == WRITING); + //assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue + + assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path + + assign done = (state == DONE); + assign error = (state == ERROR); + assign idle = (state == IDLE); + +endmodule // buffer_int diff --git a/usrp2/fifo/buffer_int_tb.v b/usrp2/fifo/buffer_int_tb.v new file mode 100644 index 000000000..df54dcc0b --- /dev/null +++ b/usrp2/fifo/buffer_int_tb.v @@ -0,0 +1,418 @@ + +module buffer_int_tb (); + + reg clk = 0; + reg rst = 1; + + initial #100 rst = 0; + always #5 clk = ~clk; + + wire en, we; + wire [8:0] addr; + wire [31:0] fifo2buf, buf2fifo; + + wire [31:0] rd_data_o; + wire [3:0] rd_flags_o; + wire rd_sop_o, rd_eop_o; + reg rd_error_i = 0, rd_read_i = 0; + + reg [31:0] wr_data_i = 0; + wire [3:0] wr_flags_i; + reg wr_eop_i = 0, wr_sop_i = 0; + reg wr_write_i = 0; + wire wr_ready_o, wr_full_o; + + reg clear = 0, write = 0, read = 0; + reg [8:0] firstline = 0, lastline = 0; + wire [3:0] step = 1; + wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; + reg go = 0; + wire done, error; + + assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i}; + assign rd_sop_o = rd_flags_o[0]; + assign rd_eop_o = rd_flags_o[1]; + + buffer_int buffer_int + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(done),.error(error), + + // Buffer Interface + .en_o(en),.we_o(we),.addr_o(addr), + .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), + + // Write FIFO Interface + .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o), + + // Read FIFO Interface + .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i) + ); + + reg ram_en = 0, ram_we = 0; + reg [8:0] ram_addr = 0; + reg [31:0] ram_data = 0; + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port + (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), + .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); + + initial + begin + @(negedge rst); + @(posedge clk); + FillRAM; + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, no wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, 2 wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,2); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then nothing after last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(3,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then done at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,0); + ReadALine; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 3 wait states, then error at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,3); + rd_error_i <= 1; + ReadALine; + rd_error_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(500,511); + $display("Testing full read, to the end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(12,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Testing full read, start to end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(505,3); + $display("Testing full read, wraparound"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(11,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(10,15); + $display("Testing Full Write, no wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,72); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(18,23); + $display("Testing Full Write, 1 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,1,101); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(27,40); + $display("Testing Partial Write, 0 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,201); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(45,200); + $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); + while(!wr_ready_o) + @(posedge clk); + wr_sop_i <= 1; wr_eop_i <= 0; + WriteLines(6,0,301); + wr_sop_i <= 0; wr_eop_i <= 1; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(55,200); + $display("Testing Partial Write, 0 wait states, then error"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,501); + wr_sop_i <= 1; wr_eop_i <= 1; + WriteALine(400); + @(posedge clk); + repeat (10) + @(posedge clk); + wr_sop_i <= 0; wr_eop_i <= 0; + + ResetBuffer; + SetBufferRead(0,82); + $display("Testing read after all the writes"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(83,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(508,4); + $display("Testing wraparound write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(9,0,601); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(506,10); + $display("Reading wraparound write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(17,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(0,511); + $display("Testing Whole Buffer write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(512,0,1000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Reading Whole Buffer write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + /* + ResetBuffer; + SetBufferWrite(5,10); + $display("Testing Write Too Many"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(12,0,2000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,15); + $display("Reading back Write Too Many"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(16,0); + repeat (10) + @(posedge clk); + */ + ResetBuffer; + SetBufferWrite(15,20); + $display("Testing Write One Less Than Full"); + while(!wr_ready_o) + @(posedge clk); + wr_sop_i <= 1; wr_eop_i <= 0; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + WriteLines(3,0,2000); + wr_sop_i <= 0; wr_eop_i <= 1; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(13,22); + $display("Reading back Write One Less Than Full"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(10,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + repeat(100) + @(posedge clk); + $finish; + end + + always @(posedge clk) + if(rd_read_i == 1'd1) + $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o); + + always @(posedge clk) + if(wr_write_i == 1'd1) + $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o); + + initial begin + $dumpfile("buffer_int_tb.lxt"); + $dumpvars(0,buffer_int_tb); + end + + task FillRAM; + begin + ram_addr <= 0; + ram_data <= 0; + @(posedge clk); + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + repeat (511) + begin + ram_addr <= ram_addr + 1; + ram_data <= ram_data + 1; + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + end + ram_en <= 0; + ram_we <= 0; + @(posedge clk); + $display("Filled the RAM"); + end + endtask // FillRAM + + task ResetBuffer; + begin + clear <= 1; read <= 0; write <= 0; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Reset"); + end + endtask // ClearBuffer + + task SetBufferWrite; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 0; write <= 1; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Write"); + end + endtask // SetBufferWrite + + task SetBufferRead; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 1; write <= 0; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Read"); + end + endtask // SetBufferRead + + task ReadALine; + begin + while(~rd_ready_o) + @(posedge clk); + #1 rd_read_i <= 1; + @(posedge clk); + rd_read_i <= 0; + end + endtask // ReadALine + + task ReadLines; + input [9:0] lines; + input [7:0] wait_states; + begin + $display("Read Lines: Number %d, Wait States %d",lines,wait_states); + repeat (lines) + begin + ReadALine; + repeat (wait_states) + @(posedge clk); + end + end + endtask // ReadLines + + task WriteALine; + input [31:0] value; + begin + while(~wr_ready_o) + @(posedge clk); + #1 wr_write_i <= 1; + wr_data_i <= value; + @(posedge clk); + wr_write_i <= 0; + end + endtask // WriteALine + + task WriteLines; + input [9:0] lines; + input [7:0] wait_states; + input [31:0] value; + begin + $display("Write Lines: Number %d, Wait States %d",lines,wait_states); + repeat(lines) + begin + value <= value + 1; + WriteALine(value); + repeat(wait_states) + @(posedge clk); + end + end + endtask // WriteLines + +endmodule // buffer_int_tb diff --git a/usrp2/fifo/buffer_pool.v b/usrp2/fifo/buffer_pool.v new file mode 100644 index 000000000..41ac1deb3 --- /dev/null +++ b/usrp2/fifo/buffer_pool.v @@ -0,0 +1,283 @@ + +// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer +// is a dual-ported RAM. Port A on each of them is indirectly connected +// to the wishbone bus by a bridge. Port B may be connected any one of the +// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus +// provides access to all 8 buffers, and also controls the connections +// between the ports and the buffers, allocating them as needed. + +// wb_adr is 16 bits -- +// bits 13:11 select which buffer +// bits 10:2 select line in buffer +// bits 1:0 are unused (32-bit access only) + +// BUF_SIZE is in address lines (i.e. log2 of number of lines). +// For S3 it should be 9 (512 words, 2KB) +// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB) + +module buffer_pool + #(parameter BUF_SIZE = 9, + parameter SET_ADDR = 64) + (input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + output wb_err_o, + output wb_rty_o, + + input stream_clk, + input stream_rst, + + input set_stb, input [7:0] set_addr, input [31:0] set_data, + output [31:0] status, + output sys_int_o, + + output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, + output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, + + // Write Interfaces + input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o, + input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o, + input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o, + input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o, + + // Read Interfaces + output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i, + output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i, + output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i, + output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i + ); + + wire [7:0] sel_a; + + wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; // ignore address 1:0, 32-bit access only + wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; // address 15:14 selects the buffer pool + + decoder_3_8 dec(.sel(which_buf),.res(sel_a)); + + genvar i; + + wire go; + + reg [2:0] port[0:7]; + reg [3:0] read_src[0:3]; + reg [3:0] write_src[0:3]; + + wire [7:0] done; + wire [7:0] error; + wire [7:0] idle; + + wire [31:0] buf_doa[0:7]; + + wire [7:0] buf_enb; + wire [7:0] buf_web; + wire [BUF_SIZE-1:0] buf_addrb[0:7]; + wire [31:0] buf_dib[0:7]; + wire [31:0] buf_dob[0:7]; + + wire [31:0] wr_data_i[0:7]; + wire [3:0] wr_flags_i[0:7]; + wire [7:0] wr_ready_i; + wire [7:0] wr_ready_o; + + wire [31:0] rd_data_o[0:7]; + wire [3:0] rd_flags_o[0:7]; + wire [7:0] rd_ready_o; + wire [7:0] rd_ready_i; + + assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; + + assign s0 = buf_addrb[0]; + assign s1 = buf_addrb[1]; + assign s2 = buf_addrb[2]; + assign s3 = buf_addrb[3]; + assign s4 = buf_addrb[4]; + assign s5 = buf_addrb[5]; + assign s6 = buf_addrb[6]; + assign s7 = buf_addrb[7]; + + wire [31:0] fifo_ctrl; + setting_reg #(.my_addr(SET_ADDR)) + sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), + .out(fifo_ctrl),.changed(go)); + + integer k; + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<8;k=k+1) + port[k] <= 4; // disabled + else + for(k=0;k<8;k=k+1) + if(go & (fifo_ctrl[31:28]==k)) + port[k] <= fifo_ctrl[27:25]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + read_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) + read_src[k] <= fifo_ctrl[31:28]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + write_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) + write_src[k] <= fifo_ctrl[31:28]; + + generate + for(i=0;i<8;i=i+1) + begin : gen_buffer + RAMB16_S36_S36 dpram + (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), + .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), + .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); + +/* + ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer + (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), + .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), + .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), + .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); + + */ + + buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int + (.clk(stream_clk),.rst(stream_rst), + .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), + .done(done[i]),.error(error[i]),.idle(idle[i]), + .en_o(buf_enb[i]), + .we_o(buf_web[i]), + .addr_o(buf_addrb[i]), + .dat_to_buf(buf_dib[i]), + .dat_from_buf(buf_dob[i]), + .wr_data_i(wr_data_i[i]), + .wr_flags_i(wr_flags_i[i]), + .wr_ready_i(wr_ready_i[i]), + .wr_ready_o(wr_ready_o[i]), + .rd_data_o(rd_data_o[i]), + .rd_flags_o(rd_flags_o[i]), + .rd_ready_o(rd_ready_o[i]), + .rd_ready_i(rd_ready_i[i]) ); + mux4 #(.WIDTH(37)) + mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]), + .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}), + .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}), + .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}), + .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}), + .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) ); + mux4 #(.WIDTH(1)) + mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]), + .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i), + .o(rd_ready_i[i])); + end // block: gen_buffer + endgenerate + + //---------------------------------------------------------------------- + // Wishbone Outputs + + // Use the following lines if ram output and mux can be made fast enough + + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + + always @(posedge wb_clk_i) + wb_ack_o <= wb_stb_i & ~wb_ack_o; + assign wb_dat_o = buf_doa[which_buf]; + + // Use this if we can't make the RAM+MUX fast enough + // reg [31:0] wb_dat_o_reg; + // reg stb_d1; + + // always @(posedge wb_clk_i) + // begin + // wb_dat_o_reg <= buf_doa[which_buf]; + // stb_d1 <= wb_stb_i; + // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); + // end + //assign wb_dat_o = wb_dat_o_reg; + + mux8 #(.WIDTH(1)) + mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr0_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr1_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr2_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr3_ready_o)); + + mux8 #(.WIDTH(37)) + mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd0_data_o,rd0_flags_o,rd0_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd1_data_o,rd1_flags_o,rd1_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd2_data_o,rd2_flags_o,rd2_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd3_data_o,rd3_flags_o,rd3_ready_o})); + + assign sys_int_o = (|error) | (|done); + +endmodule // buffer_pool diff --git a/usrp2/fifo/buffer_pool_tb.v b/usrp2/fifo/buffer_pool_tb.v new file mode 100644 index 000000000..91a01d268 --- /dev/null +++ b/usrp2/fifo/buffer_pool_tb.v @@ -0,0 +1,58 @@ + +module buffer_pool_tb(); + + wire wb_clk_i; + wire wb_rst_i; + wire wb_we_i; + wire wb_stb_i; + wire [15:0] wb_adr_i; + wire [31:0] wb_dat_i; + wire [31:0] wb_dat_o; + wire wb_ack_o; + wire wb_err_o; + wire wb_rty_o; + + wire stream_clk, stream_rst; + + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data; + wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire wr0_ready, wr1_ready, wr2_ready, wr3_ready; + wire rd0_ready, rd1_ready, rd2_ready, rd3_ready; + wire wr0_write, wr1_write, wr2_write, wr3_write; + wire rd0_read, rd1_read, rd2_read, rd3_read; + + buffer_pool dut + (.wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_stb_i), + .wb_adr_i(wb_adr_i), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_ack_o(wb_ack_o), + .wb_err_o(wb_err_o), + .wb_rty_o(wb_rty_o), + + .stream_clk(stream_clk), + .stream_rst(stream_rst), + + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + + .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready), + .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready), + .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready), + .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready), + + .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready), + .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready), + .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready), + .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready) + ); + +endmodule // buffer_pool_tb diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v new file mode 100644 index 000000000..5f9aeff9b --- /dev/null +++ b/usrp2/fifo/fifo19_to_fifo36.v @@ -0,0 +1,76 @@ + +module fifo19_to_fifo36 + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); + + reg f36_sof, f36_eof, f36_occ; + + reg [1:0] state; + reg [15:0] dat0, dat1; + + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; + + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + + always @(posedge clk) + if(f19_src_rdy_i & ((state==0)|xfer_out)) + f36_sof <= f19_sof; + + always @(posedge clk) + if(f19_src_rdy_i & ((state != 2)|xfer_out)) + f36_eof <= f19_eof; + + always @(posedge clk) // FIXME check this + if(f19_eof) + f36_occ <= {state[0],f19_occ}; + else + f36_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(f19_src_rdy_i) + case(state) + 0 : + if(f19_eof) + state <= 2; + else + state <= 1; + 1 : + state <= 2; + 2 : + if(xfer_out) + if(~f19_eof) + state <= 1; + // remain in state 2 if we are at eof + endcase // case(state) + else + if(xfer_out) + state <= 0; + + always @(posedge clk) + if(f19_src_rdy_i & (state==1)) + dat1 <= f19_datain; + + always @(posedge clk) + if(f19_src_rdy_i & ((state==0) | xfer_out)) + dat0 <= f19_datain; + + assign f19_dst_rdy_o = xfer_out | (state != 2); + assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_src_rdy_o = (state == 2); + + assign debug = state; + +endmodule // fifo19_to_fifo36 diff --git a/usrp2/fifo/fifo19_to_ll8.v b/usrp2/fifo/fifo19_to_ll8.v new file mode 100644 index 000000000..4707f7523 --- /dev/null +++ b/usrp2/fifo/fifo19_to_ll8.v @@ -0,0 +1,53 @@ + +module fifo19_to_ll8 + (input clk, input reset, input clear, + input [18:0] f19_data, + input f19_src_rdy_i, + output f19_dst_rdy_o, + + output reg [7:0] ll_data, + output ll_sof_n, + output ll_eof_n, + output ll_src_rdy_n, + input ll_dst_rdy_n); + + wire ll_sof, ll_eof, ll_src_rdy; + assign ll_sof_n = ~ll_sof; + assign ll_eof_n = ~ll_eof; + assign ll_src_rdy_n = ~ll_src_rdy; + wire ll_dst_rdy = ~ll_dst_rdy_n; + + wire f19_sof = f19_data[16]; + wire f19_eof = f19_data[17]; + wire f19_occ = f19_data[18]; + + wire advance, end_early; + reg state; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(advance) + if(ll_eof) + state <= 0; + else + state <= state + 1; + + always @* + case(state) + 0 : ll_data = f19_data[15:8]; + 1 : ll_data = f19_data[7:0]; + default : ll_data = f19_data[15:8]; + endcase // case (state) + + assign ll_sof = (state==0) & f19_sof; + assign ll_eof = f19_eof & ((f19_occ==1)|(state==1)); + + assign ll_src_rdy = f19_src_rdy_i; + + assign advance = ll_src_rdy & ll_dst_rdy; + assign f19_dst_rdy_o = advance & ((state==1)|ll_eof); + +endmodule // fifo19_to_ll8 + diff --git a/usrp2/fifo/fifo36_to_fifo18.v b/usrp2/fifo/fifo36_to_fifo18.v new file mode 100644 index 000000000..b636ab9ca --- /dev/null +++ b/usrp2/fifo/fifo36_to_fifo18.v @@ -0,0 +1,40 @@ + +module fifo36_to_fifo18 + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [17:0] f18_dataout, + output f18_src_rdy_o, + input f18_dst_rdy_i ); + + wire f36_sof = f36_datain[32]; + wire f36_eof = f36_datain[33]; + wire f36_occ = f36_datain[35:34]; + + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + assign f18_dataout[16] = phase ? 0 : f36_sof; + assign f18_dataout[17] = phase ? f36_eof : half_line; + + assign f18_src_rdy_o = f36_src_rdy_i; + assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; + + wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + + always @(posedge clk) + if(reset) + phase <= 0; + else if(f36_xfer) + phase <= 0; + else if(f18_xfer) + phase <= 1; + + +endmodule // fifo36_to_fifo18 + diff --git a/usrp2/fifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v new file mode 100644 index 000000000..de249aaeb --- /dev/null +++ b/usrp2/fifo/fifo36_to_fifo19.v @@ -0,0 +1,41 @@ + +module fifo36_to_fifo19 + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + wire f36_sof = f36_datain[32]; + wire f36_eof = f36_datain[33]; + wire f36_occ = f36_datain[35:34]; + + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + assign f19_dataout[16] = phase ? 0 : f36_sof; + assign f19_dataout[17] = phase ? f36_eof : half_line; + assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); + + assign f19_src_rdy_o = f36_src_rdy_i; + assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + + always @(posedge clk) + if(reset) + phase <= 0; + else if(f36_xfer) + phase <= 0; + else if(f19_xfer) + phase <= 1; + + +endmodule // fifo36_to_fifo19 + diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v new file mode 100644 index 000000000..0dee1dfc6 --- /dev/null +++ b/usrp2/fifo/fifo36_to_ll8.v @@ -0,0 +1,60 @@ + +module fifo36_to_ll8 + (input clk, input reset, input clear, + input [35:0] f36_data, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output reg [7:0] ll_data, + output ll_sof_n, + output ll_eof_n, + output ll_src_rdy_n, + input ll_dst_rdy_n, + + output [31:0] debug); + + wire ll_sof, ll_eof, ll_src_rdy; + assign ll_sof_n = ~ll_sof; + assign ll_eof_n = ~ll_eof; + assign ll_src_rdy_n = ~ll_src_rdy; + wire ll_dst_rdy = ~ll_dst_rdy_n; + + wire f36_sof = f36_data[32]; + wire f36_eof = f36_data[33]; + wire f36_occ = f36_data[35:34]; + wire advance, end_early; + reg [1:0] state; + assign debug = {29'b0,state}; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(advance) + if(ll_eof) + state <= 0; + else + state <= state + 1; + + always @* + case(state) + 0 : ll_data = f36_data[31:24]; + 1 : ll_data = f36_data[23:16]; + 2 : ll_data = f36_data[15:8]; + 3 : ll_data = f36_data[7:0]; + default : ll_data = f36_data[31:24]; + endcase // case (state) + + assign ll_sof = (state==0) & f36_sof; + assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) | + ((state==1)&(f36_occ==2)) | + ((state==2)&(f36_occ==3)) | + (state==3)); + + assign ll_src_rdy = f36_src_rdy_i; + + assign advance = ll_src_rdy & ll_dst_rdy; + assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); + assign debug = state; + +endmodule // ll8_to_fifo36 diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v new file mode 100644 index 000000000..34c85ccb4 --- /dev/null +++ b/usrp2/fifo/fifo_2clock.v @@ -0,0 +1,117 @@ + +// FIXME ignores the AWIDTH (fifo size) parameter + +module fifo_2clock + #(parameter WIDTH=36, SIZE=6) + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input arst); + + wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels + wire full, empty, write, read; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + assign write = src_rdy_i & dst_rdy_o; + assign read = src_rdy_o & dst_rdy_i; + + generate + if(WIDTH==36) + if(SIZE==9) + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==11) + fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==6) + fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19)|(WIDTH==18)) + if(SIZE==4) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + endgenerate + + assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; + assign space = ((1<<SIZE)+1)-level_wclk; + +endmodule // fifo_2clock + +/* +`else + // ISE sucks, so the following doesn't work properly + + reg [AWIDTH-1:0] wr_addr, rd_addr; + wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk; + wire [AWIDTH-1:0] next_rd_addr; + wire enb_read; + + // Write side management + wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1; + always @(posedge wclk or posedge arst) + if(arst) + wr_addr <= 0; + else if(write) + wr_addr <= next_wr_addr; + assign full = (next_wr_addr == rd_addr_wclk); + + // RAM for data storage. Data out is registered, complicating the + // read side logic + ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram + (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(), + .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) ); + + // Read side management + reg data_valid; + assign empty = ~data_valid; + assign next_rd_addr = rd_addr + data_valid; + assign enb_read = read | ~data_valid; + + always @(posedge rclk or posedge arst) + if(arst) + rd_addr <= 0; + else if(read) + rd_addr <= rd_addr + 1; + + always @(posedge rclk or posedge arst) + if(arst) + data_valid <= 0; + else + if(read & (next_rd_addr == wr_addr_rclk)) + data_valid <= 0; + else if(next_rd_addr != wr_addr_rclk) + data_valid <= 1; + + // Send pointers across clock domains via gray code + gray_send #(.WIDTH(AWIDTH)) send_wr_addr + (.clk_in(wclk),.addr_in(wr_addr), + .clk_out(rclk),.addr_out(wr_addr_rclk) ); + + gray_send #(.WIDTH(AWIDTH)) send_rd_addr + (.clk_in(rclk),.addr_in(rd_addr), + .clk_out(wclk),.addr_out(rd_addr_wclk) ); + + // Generate fullness info, these are approximate and may be delayed + // and are only for higher-level flow control. + // Only full and empty are guaranteed exact. + always @(posedge wclk) + level_wclk <= wr_addr - rd_addr_wclk; + always @(posedge rclk) + level_rclk <= wr_addr_rclk - rd_addr; +`endif +endmodule // fifo_2clock + +*/ diff --git a/usrp2/fifo/fifo_2clock_cascade.v b/usrp2/fifo/fifo_2clock_cascade.v new file mode 100644 index 000000000..5ce726977 --- /dev/null +++ b/usrp2/fifo/fifo_2clock_cascade.v @@ -0,0 +1,35 @@ + +module fifo_2clock_cascade + #(parameter WIDTH=32, SIZE=9) + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input arst); + + wire [WIDTH-1:0] data_int1, data_int2; + wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; + wire [SIZE-1:0] level_wclk, level_rclk; + wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; + wire [15:0] l_space, l_occupied; + + fifo_short #(.WIDTH(WIDTH)) shortfifo + (.clk(wclk), .reset(arst), .clear(0), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), + .space(s1_space), .occupied(s1_occupied) ); + + fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock + (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space), + .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied), + .arst(arst) ); + + fifo_short #(.WIDTH(WIDTH)) shortfifo2 + (.clk(rclk), .reset(arst), .clear(0), + .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(s2_space), .occupied(s2_occupied)); + + // Be conservative -- Only advertise space from input side of fifo, occupied from output side + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + +endmodule // fifo_2clock_cascade diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v new file mode 100644 index 000000000..fdd8449bc --- /dev/null +++ b/usrp2/fifo/fifo_cascade.v @@ -0,0 +1,52 @@ + + +// This FIFO exists to provide an intermediate point for the data on its +// long trek from one RAM (in the buffer pool) to another (in the longfifo) +// The shortfifo is more flexible in its placement since it is based on +// distributed RAM + +// This one has the shortfifo on both the in and out sides. +module fifo_cascade + #(parameter WIDTH=32, SIZE=9) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + output [15:0] space, + output [15:0] occupied); + + wire [WIDTH-1:0] data_int, data_int2; + wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2; + + wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; + wire [15:0] l_space, l_occupied; + + fifo_short #(.WIDTH(WIDTH)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1), + .space(s1_space),.occupied(s1_occupied) ); + + fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1), + .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2), + .space(l_space),.occupied(l_occupied) ); + + fifo_short #(.WIDTH(WIDTH)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(s2_space),.occupied(s2_occupied) ); + + assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space; + assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied; + +endmodule // cascadefifo2 + + + + diff --git a/usrp2/fifo/fifo_long.v b/usrp2/fifo/fifo_long.v new file mode 100644 index 000000000..0426779f6 --- /dev/null +++ b/usrp2/fifo/fifo_long.v @@ -0,0 +1,148 @@ + +// FIFO intended to be interchangeable with shortfifo, but +// based on block ram instead of SRL16's +// only one clock domain + +// Port A is write port, Port B is read port + +module fifo_long + #(parameter WIDTH=32, SIZE=9) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + + output reg [15:0] space, + output reg [15:0] occupied); + + wire write = src_rdy_i & dst_rdy_o; + wire read = dst_rdy_i & src_rdy_o; + wire full, empty; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + + // Read side states + localparam EMPTY = 0; + localparam PRE_READ = 1; + localparam READING = 2; + + reg [SIZE-1:0] wr_addr, rd_addr; + reg [1:0] read_state; + + reg empty_reg, full_reg; + always @(posedge clk) + if(reset) + wr_addr <= 0; + else if(clear) + wr_addr <= 0; + else if(write) + wr_addr <= wr_addr + 1; + + ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE)) + ram (.clka(clk), + .ena(1'b1), + .wea(write), + .addra(wr_addr), + .dia(datain), + .doa(), + + .clkb(clk), + .enb((read_state==PRE_READ)|read), + .web(0), + .addrb(rd_addr), + .dib(0), + .dob(dataout)); + + always @(posedge clk) + if(reset) + begin + read_state <= EMPTY; + rd_addr <= 0; + empty_reg <= 1; + end + else + if(clear) + begin + read_state <= EMPTY; + rd_addr <= 0; + empty_reg <= 1; + end + else + case(read_state) + EMPTY : + if(write) + begin + //rd_addr <= wr_addr; + read_state <= PRE_READ; + end + PRE_READ : + begin + read_state <= READING; + empty_reg <= 0; + rd_addr <= rd_addr + 1; + end + + READING : + if(read) + if(rd_addr == wr_addr) + begin + empty_reg <= 1; + if(write) + read_state <= PRE_READ; + else + read_state <= EMPTY; + end + else + rd_addr <= rd_addr + 1; + endcase // case(read_state) + + wire [SIZE-1:0] dont_write_past_me = rd_addr - 3; + wire becoming_full = wr_addr == dont_write_past_me; + + always @(posedge clk) + if(reset) + full_reg <= 0; + else if(clear) + full_reg <= 0; + else if(read & ~write) + full_reg <= 0; + //else if(write & ~read & (wr_addr == (rd_addr-3))) + else if(write & ~read & becoming_full) + full_reg <= 1; + + //assign empty = (read_state != READING); + assign empty = empty_reg; + + // assign full = ((rd_addr - 1) == wr_addr); + assign full = full_reg; + + ////////////////////////////////////////////// + // space and occupied are for diagnostics only + // not guaranteed exact + + localparam NUMLINES = (1<<SIZE)-2; + always @(posedge clk) + if(reset) + space <= NUMLINES; + else if(clear) + space <= NUMLINES; + else if(read & ~write) + space <= space + 1; + else if(write & ~read) + space <= space - 1; + + always @(posedge clk) + if(reset) + occupied <= 0; + else if(clear) + occupied <= 0; + else if(read & ~write) + occupied <= occupied - 1; + else if(write & ~read) + occupied <= occupied + 1; + +endmodule // fifo_long diff --git a/usrp2/fifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd new file mode 100644 index 000000000..796889e7d --- /dev/null +++ b/usrp2/fifo/fifo_new_tb.vcd @@ -0,0 +1,5506 @@ +$date + Thu Mar 19 17:21:11 2009 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module fifo_new_tb $end +$var wire 1 ! dst_rdy_f36i $end +$var wire 36 " f36_in [35:0] $end +$var wire 36 # i1 [35:0] $end +$var wire 1 $ i1_dr $end +$var wire 1 % i1_sr $end +$var wire 19 & i2 [18:0] $end +$var wire 1 ' i2_dr $end +$var wire 1 ( i2_sr $end +$var wire 19 ) i3 [18:0] $end +$var wire 1 * i3_dr $end +$var wire 1 + i3_sr $end +$var wire 36 , i4 [35:0] $end +$var wire 1 - i4_sr $end +$var wire 8 . ll_data [7:0] $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 0 ll_eof_n $end +$var wire 1 1 ll_sof_n $end +$var wire 1 2 ll_src_rdy_n $end +$var reg 1 3 clear $end +$var reg 1 4 clk $end +$var reg 16 5 count [15:0] $end +$var reg 1 6 dst_rdy_f36o $end +$var reg 32 7 f36_data [31:0] $end +$var reg 1 8 f36_eof $end +$var reg 2 9 f36_occ [1:0] $end +$var reg 1 : f36_sof $end +$var reg 1 ; i4_dr $end +$var reg 1 < rst $end +$var reg 1 = src_rdy_f36i $end +$scope module fifo_short1 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 36 @ datain [35:0] $end +$var wire 36 A dataout [35:0] $end +$var wire 1 $ dst_rdy_i $end +$var wire 1 ! dst_rdy_o $end +$var wire 1 B read $end +$var wire 1 C reset $end +$var wire 1 D src_rdy_i $end +$var wire 1 % src_rdy_o $end +$var wire 1 E write $end +$var reg 4 F a [3:0] $end +$var reg 1 G empty $end +$var reg 1 H full $end +$var reg 5 I occupied [4:0] $end +$var reg 5 J space [4:0] $end +$scope begin gen_srl16[0] $end +$scope module srl16e $end +$var wire 1 K A0 $end +$var wire 1 L A1 $end +$var wire 1 M A2 $end +$var wire 1 N A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 O D $end +$var wire 1 P Q $end +$var reg 16 Q data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[1] $end +$scope module srl16e $end +$var wire 1 R A0 $end +$var wire 1 S A1 $end +$var wire 1 T A2 $end +$var wire 1 U A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 V D $end +$var wire 1 W Q $end +$var reg 16 X data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[2] $end +$scope module srl16e $end +$var wire 1 Y A0 $end +$var wire 1 Z A1 $end +$var wire 1 [ A2 $end +$var wire 1 \ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ] D $end +$var wire 1 ^ Q $end +$var reg 16 _ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[3] $end +$scope module srl16e $end +$var wire 1 ` A0 $end +$var wire 1 a A1 $end +$var wire 1 b A2 $end +$var wire 1 c A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 d D $end +$var wire 1 e Q $end +$var reg 16 f data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[4] $end +$scope module srl16e $end +$var wire 1 g A0 $end +$var wire 1 h A1 $end +$var wire 1 i A2 $end +$var wire 1 j A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 k D $end +$var wire 1 l Q $end +$var reg 16 m data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[5] $end +$scope module srl16e $end +$var wire 1 n A0 $end +$var wire 1 o A1 $end +$var wire 1 p A2 $end +$var wire 1 q A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 r D $end +$var wire 1 s Q $end +$var reg 16 t data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[6] $end +$scope module srl16e $end +$var wire 1 u A0 $end +$var wire 1 v A1 $end +$var wire 1 w A2 $end +$var wire 1 x A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 y D $end +$var wire 1 z Q $end +$var reg 16 { data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[7] $end +$scope module srl16e $end +$var wire 1 | A0 $end +$var wire 1 } A1 $end +$var wire 1 ~ A2 $end +$var wire 1 !" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 "" D $end +$var wire 1 #" Q $end +$var reg 16 $" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[8] $end +$scope module srl16e $end +$var wire 1 %" A0 $end +$var wire 1 &" A1 $end +$var wire 1 '" A2 $end +$var wire 1 (" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 )" D $end +$var wire 1 *" Q $end +$var reg 16 +" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[9] $end +$scope module srl16e $end +$var wire 1 ," A0 $end +$var wire 1 -" A1 $end +$var wire 1 ." A2 $end +$var wire 1 /" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 0" D $end +$var wire 1 1" Q $end +$var reg 16 2" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[10] $end +$scope module srl16e $end +$var wire 1 3" A0 $end +$var wire 1 4" A1 $end +$var wire 1 5" A2 $end +$var wire 1 6" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 7" D $end +$var wire 1 8" Q $end +$var reg 16 9" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[11] $end +$scope module srl16e $end +$var wire 1 :" A0 $end +$var wire 1 ;" A1 $end +$var wire 1 <" A2 $end +$var wire 1 =" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 >" D $end +$var wire 1 ?" Q $end +$var reg 16 @" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[12] $end +$scope module srl16e $end +$var wire 1 A" A0 $end +$var wire 1 B" A1 $end +$var wire 1 C" A2 $end +$var wire 1 D" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 E" D $end +$var wire 1 F" Q $end +$var reg 16 G" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[13] $end +$scope module srl16e $end +$var wire 1 H" A0 $end +$var wire 1 I" A1 $end +$var wire 1 J" A2 $end +$var wire 1 K" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 L" D $end +$var wire 1 M" Q $end +$var reg 16 N" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[14] $end +$scope module srl16e $end +$var wire 1 O" A0 $end +$var wire 1 P" A1 $end +$var wire 1 Q" A2 $end +$var wire 1 R" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 S" D $end +$var wire 1 T" Q $end +$var reg 16 U" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[15] $end +$scope module srl16e $end +$var wire 1 V" A0 $end +$var wire 1 W" A1 $end +$var wire 1 X" A2 $end +$var wire 1 Y" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 Z" D $end +$var wire 1 [" Q $end +$var reg 16 \" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[16] $end +$scope module srl16e $end +$var wire 1 ]" A0 $end +$var wire 1 ^" A1 $end +$var wire 1 _" A2 $end +$var wire 1 `" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 a" D $end +$var wire 1 b" Q $end +$var reg 16 c" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[17] $end +$scope module srl16e $end +$var wire 1 d" A0 $end +$var wire 1 e" A1 $end +$var wire 1 f" A2 $end +$var wire 1 g" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 h" D $end +$var wire 1 i" Q $end +$var reg 16 j" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[18] $end +$scope module srl16e $end +$var wire 1 k" A0 $end +$var wire 1 l" A1 $end +$var wire 1 m" A2 $end +$var wire 1 n" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 o" D $end +$var wire 1 p" Q $end +$var reg 16 q" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[19] $end +$scope module srl16e $end +$var wire 1 r" A0 $end +$var wire 1 s" A1 $end +$var wire 1 t" A2 $end +$var wire 1 u" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 v" D $end +$var wire 1 w" Q $end +$var reg 16 x" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[20] $end +$scope module srl16e $end +$var wire 1 y" A0 $end +$var wire 1 z" A1 $end +$var wire 1 {" A2 $end +$var wire 1 |" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 }" D $end +$var wire 1 ~" Q $end +$var reg 16 !# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[21] $end +$scope module srl16e $end +$var wire 1 "# A0 $end +$var wire 1 ## A1 $end +$var wire 1 $# A2 $end +$var wire 1 %# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 &# D $end +$var wire 1 '# Q $end +$var reg 16 (# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[22] $end +$scope module srl16e $end +$var wire 1 )# A0 $end +$var wire 1 *# A1 $end +$var wire 1 +# A2 $end +$var wire 1 ,# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 -# D $end +$var wire 1 .# Q $end +$var reg 16 /# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[23] $end +$scope module srl16e $end +$var wire 1 0# A0 $end +$var wire 1 1# A1 $end +$var wire 1 2# A2 $end +$var wire 1 3# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 4# D $end +$var wire 1 5# Q $end +$var reg 16 6# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[24] $end +$scope module srl16e $end +$var wire 1 7# A0 $end +$var wire 1 8# A1 $end +$var wire 1 9# A2 $end +$var wire 1 :# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ;# D $end +$var wire 1 <# Q $end +$var reg 16 =# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[25] $end +$scope module srl16e $end +$var wire 1 ># A0 $end +$var wire 1 ?# A1 $end +$var wire 1 @# A2 $end +$var wire 1 A# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 B# D $end +$var wire 1 C# Q $end +$var reg 16 D# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[26] $end +$scope module srl16e $end +$var wire 1 E# A0 $end +$var wire 1 F# A1 $end +$var wire 1 G# A2 $end +$var wire 1 H# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 I# D $end +$var wire 1 J# Q $end +$var reg 16 K# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[27] $end +$scope module srl16e $end +$var wire 1 L# A0 $end +$var wire 1 M# A1 $end +$var wire 1 N# A2 $end +$var wire 1 O# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 P# D $end +$var wire 1 Q# Q $end +$var reg 16 R# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[28] $end +$scope module srl16e $end +$var wire 1 S# A0 $end +$var wire 1 T# A1 $end +$var wire 1 U# A2 $end +$var wire 1 V# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 W# D $end +$var wire 1 X# Q $end +$var reg 16 Y# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[29] $end +$scope module srl16e $end +$var wire 1 Z# A0 $end +$var wire 1 [# A1 $end +$var wire 1 \# A2 $end +$var wire 1 ]# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ^# D $end +$var wire 1 _# Q $end +$var reg 16 `# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[30] $end +$scope module srl16e $end +$var wire 1 a# A0 $end +$var wire 1 b# A1 $end +$var wire 1 c# A2 $end +$var wire 1 d# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 e# D $end +$var wire 1 f# Q $end +$var reg 16 g# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[31] $end +$scope module srl16e $end +$var wire 1 h# A0 $end +$var wire 1 i# A1 $end +$var wire 1 j# A2 $end +$var wire 1 k# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 l# D $end +$var wire 1 m# Q $end +$var reg 16 n# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[32] $end +$scope module srl16e $end +$var wire 1 o# A0 $end +$var wire 1 p# A1 $end +$var wire 1 q# A2 $end +$var wire 1 r# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 s# D $end +$var wire 1 t# Q $end +$var reg 16 u# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[33] $end +$scope module srl16e $end +$var wire 1 v# A0 $end +$var wire 1 w# A1 $end +$var wire 1 x# A2 $end +$var wire 1 y# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 z# D $end +$var wire 1 {# Q $end +$var reg 16 |# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[34] $end +$scope module srl16e $end +$var wire 1 }# A0 $end +$var wire 1 ~# A1 $end +$var wire 1 !$ A2 $end +$var wire 1 "$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 #$ D $end +$var wire 1 $$ Q $end +$var reg 16 %$ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[35] $end +$scope module srl16e $end +$var wire 1 &$ A0 $end +$var wire 1 '$ A1 $end +$var wire 1 ($ A2 $end +$var wire 1 )$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 *$ D $end +$var wire 1 +$ Q $end +$var reg 16 ,$ data [15:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module fifo36_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 -$ f19_dataout [18:0] $end +$var wire 1 ' f19_dst_rdy_i $end +$var wire 1 ( f19_src_rdy_o $end +$var wire 1 .$ f19_xfer $end +$var wire 36 /$ f36_datain [35:0] $end +$var wire 1 $ f36_dst_rdy_o $end +$var wire 1 0$ f36_eof $end +$var wire 1 1$ f36_occ $end +$var wire 1 2$ f36_sof $end +$var wire 1 % f36_src_rdy_i $end +$var wire 1 3$ f36_xfer $end +$var wire 1 4$ half_line $end +$var wire 1 C reset $end +$var reg 1 5$ phase $end +$upscope $end +$scope module fifo19_to_ll8 $end +$var wire 1 6$ advance $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 7$ f19_data [18:0] $end +$var wire 1 ' f19_dst_rdy_o $end +$var wire 1 8$ f19_eof $end +$var wire 1 9$ f19_occ $end +$var wire 1 :$ f19_sof $end +$var wire 1 ( f19_src_rdy_i $end +$var wire 1 ;$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 <$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 =$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 >$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var reg 8 ?$ ll_data [7:0] $end +$var reg 1 @$ state $end +$upscope $end +$scope module ll8_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 A$ f19_data [18:0] $end +$var wire 1 * f19_dst_rdy_i $end +$var wire 1 + f19_src_rdy_o $end +$var wire 8 B$ ll_data [7:0] $end +$var wire 1 C$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 D$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 E$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 F$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var wire 1 G$ xfer_out $end +$var reg 8 H$ dat0 [7:0] $end +$var reg 8 I$ dat1 [7:0] $end +$var reg 1 J$ f19_eof $end +$var reg 1 K$ f19_occ $end +$var reg 1 L$ f19_sof $end +$var reg 2 M$ state [1:0] $end +$upscope $end +$scope module fifo19_to_fifo36 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 N$ f19_datain [18:0] $end +$var wire 1 * f19_dst_rdy_o $end +$var wire 1 O$ f19_eof $end +$var wire 1 P$ f19_occ $end +$var wire 1 Q$ f19_sof $end +$var wire 1 + f19_src_rdy_i $end +$var wire 36 R$ f36_dataout [35:0] $end +$var wire 1 S$ f36_dst_rdy_i $end +$var wire 1 - f36_src_rdy_o $end +$var wire 1 C reset $end +$var wire 1 T$ xfer_out $end +$var reg 16 U$ dat0 [15:0] $end +$var reg 16 V$ dat1 [15:0] $end +$var reg 1 W$ f36_eof $end +$var reg 1 X$ f36_occ $end +$var reg 1 Y$ f36_sof $end +$var reg 2 Z$ state [1:0] $end +$upscope $end +$scope task PutPacketInFIFO36 $end +$var reg 32 [$ data_len [31:0] $end +$var reg 32 \$ data_start [31:0] $end +$upscope $end +$scope task ReadFromFIFO36 $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx \$ +bx [$ +bx Z$ +xY$ +xX$ +xW$ +bx V$ +bx U$ +0T$ +0S$ +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ +xQ$ +xP$ +xO$ +bx N$ +bx M$ +xL$ +xK$ +xJ$ +bx I$ +bx H$ +xG$ +xF$ +xE$ +xD$ +xC$ +bx B$ +bx A$ +x@$ +bx ?$ +x>$ +x=$ +x<$ +x;$ +x:$ +x9$ +x8$ +bx 7$ +x6$ +x5$ +x4$ +x3$ +x2$ +x1$ +x0$ +bx /$ +x.$ +bx -$ +b0 ,$ +x+$ +0*$ +x)$ +x($ +x'$ +x&$ +b0 %$ +x$$ +0#$ +x"$ +x!$ +x~# +x}# +b0 |# +x{# +0z# +xy# +xx# +xw# +xv# +b0 u# +xt# +0s# +xr# +xq# +xp# +xo# +b0 n# +xm# +0l# +xk# +xj# +xi# +xh# +b0 g# +xf# +0e# +xd# +xc# +xb# +xa# +b0 `# +x_# +0^# +x]# +x\# +x[# +xZ# +b0 Y# +xX# +0W# +xV# +xU# +xT# +xS# +b0 R# +xQ# +0P# +xO# +xN# +xM# +xL# +b0 K# +xJ# +0I# +xH# +xG# +xF# +xE# +b0 D# +xC# +0B# +xA# +x@# +x?# +x># +b0 =# +x<# +0;# +x:# +x9# +x8# +x7# +b0 6# +x5# +04# +x3# +x2# +x1# +x0# +b0 /# +x.# +0-# +x,# +x+# +x*# +x)# +b0 (# +x'# +0&# +x%# +x$# +x## +x"# +b0 !# +x~" +0}" +x|" +x{" +xz" +xy" +b0 x" +xw" +0v" +xu" +xt" +xs" +xr" +b0 q" +xp" +0o" +xn" +xm" +xl" +xk" +b0 j" +xi" +0h" +xg" +xf" +xe" +xd" +b0 c" +xb" +0a" +x`" +x_" +x^" +x]" +b0 \" +x[" +0Z" +xY" +xX" +xW" +xV" +b0 U" +xT" +0S" +xR" +xQ" +xP" +xO" +b0 N" +xM" +0L" +xK" +xJ" +xI" +xH" +b0 G" +xF" +0E" +xD" +xC" +xB" +xA" +b0 @" +x?" +0>" +x=" +x<" +x;" +x:" +b0 9" +x8" +07" +x6" +x5" +x4" +x3" +b0 2" +x1" +00" +x/" +x." +x-" +x," +b0 +" +x*" +0)" +x(" +x'" +x&" +x%" +b0 $" +x#" +0"" +x!" +x~ +x} +x| +b0 { +xz +0y +xx +xw +xv +xu +b0 t +xs +0r +xq +xp +xo +xn +b0 m +xl +0k +xj +xi +xh +xg +b0 f +xe +0d +xc +xb +xa +x` +b0 _ +x^ +0] +x\ +x[ +xZ +xY +b0 X +xW +0V +xU +xT +xS +xR +b0 Q +xP +0O +xN +xM +xL +xK +bx J +bx I +xH +xG +bx F +0E +0D +1C +xB +bx A +b0 @ +0? +0> +0= +1< +0; +0: +b0 9 +08 +b0 7 +06 +bx 5 +04 +03 +x2 +x1 +x0 +x/ +bx . +x- +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx , +x+ +x* +bx ) +x( +x' +bx & +x% +x$ +bx # +b0 " +x! +$end +#50000000000000 +0D$ +10 +0E$ +0<$ +11 +08$ +09$ +0=$ +0$ +b0 ?$ +b0 . +b0 B$ +0:$ +0' +0F$ +04$ +01$ +b0 & +b0 -$ +b0 7$ +1;$ +0.$ +06$ +12 +03$ +0B +02$ +00$ +0/ +1! +0>$ +0( +0% +0K +0P +0L +0M +0N +0R +0W +0S +0T +0U +0Y +0^ +0Z +0[ +0\ +0` +0e +0a +0b +0c +0g +0l +0h +0i +0j +0n +0s +0o +0p +0q +0u +0z +0v +0w +0x +0| +0#" +0} +0~ +0!" +0%" +0*" +0&" +0'" +0(" +0," +01" +0-" +0." +0/" +03" +08" +04" +05" +06" +0:" +0?" +0;" +0<" +0=" +0A" +0F" +0B" +0C" +0D" +0H" +0M" +0I" +0J" +0K" +0O" +0T" +0P" +0Q" +0R" +0V" +0[" +0W" +0X" +0Y" +0]" +0b" +0^" +0_" +0`" +0d" +0i" +0e" +0f" +0g" +0k" +0p" +0l" +0m" +0n" +0r" +0w" +0s" +0t" +0u" +0y" +0~" +0z" +0{" +0|" +0"# +0'# +0## +0$# +0%# +0)# +0.# +0*# +0+# +0,# +00# +05# +01# +02# +03# +07# +0<# +08# +09# +0:# +0># +0C# +0?# +0@# +0A# +0E# +0J# +0F# +0G# +0H# +0L# +0Q# +0M# +0N# +0O# +0S# +0X# +0T# +0U# +0V# +0Z# +0_# +0[# +0\# +0]# +0a# +0f# +0b# +0c# +0d# +0h# +0m# +0i# +0j# +0k# +0o# +0t# +0p# +0q# +0r# +0v# +0{# +0w# +0x# +0y# +0}# +0$$ +0~# +0!$ +0"$ +0&$ +0+$ +b0 # +b0 A +b0 /$ +0'$ +0($ +0)$ +0P$ +1C$ +0G$ +1* +0H +1G +b0 F +b10000 J +b0 I +05$ +0@$ +0K$ +b0xxxxxxxxxxxxxxxxxx ) +b0xxxxxxxxxxxxxxxxxx A$ +b0xxxxxxxxxxxxxxxxxx N$ +b0 M$ +0+ +0X$ +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx , +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ +b0 Z$ +0- +14 +1? +#100000000000000 +04 +0? +#150000000000000 +14 +1? +#200000000000000 +04 +0? +#250000000000000 +14 +1? +#300000000000000 +04 +0? +#350000000000000 +14 +1? +#400000000000000 +04 +0? +#450000000000000 +14 +1? +#500000000000000 +04 +0? +#550000000000000 +14 +1? +#600000000000000 +04 +0? +#650000000000000 +14 +1? +#700000000000000 +04 +0? +#750000000000000 +14 +1? +#800000000000000 +04 +0? +#850000000000000 +14 +1? +#900000000000000 +04 +0? +#950000000000000 +14 +1? +#1000000000000000 +04 +0? +0< +0C +#1050000000000000 +14 +1? +#1100000000000000 +04 +0? +#1150000000000000 +1k +1y +1"" +1S" +1Z" +1}" +1&# +14# +1^# +1l# +1s# +1E +1: +b10100000101100001100000011010000 7 +b110100000101100001100000011010000 " +b110100000101100001100000011010000 @ +1= +1D +b100 5 +b1100 [$ +b10100000101100001100000011010000 \$ +14 +1? +#1200000000000000 +04 +0? +#1250000000000000 +1F$ +16$ +02 +1>$ +1( +1% +1O +1)" +1a" +1;# +0s# +0G +b1111 J +b1 I +b1000 5 +b10100001101100011100000111010001 7 +0: +b10100001101100011100000111010001 " +b10100001101100011100000111010001 @ +14 +1? +#1250000000000100 +1E$ +01 +1=$ +b10100000 ?$ +b10100000 . +b10100000 B$ +1:$ +b11010000010110000 & +b11010000010110000 -$ +b11010000010110000 7$ +12$ +b1 m +1l +b1 { +1z +b1 $" +1#" +b1 U" +1T" +b1 \" +1[" +b1 !# +1~" +b1 (# +1'# +b1 6# +15# +b1 `# +1_# +b1 n# +1m# +b1 u# +1t# +b110100000101100001100000011010000 # +b110100000101100001100000011010000 A +b110100000101100001100000011010000 /$ +#1300000000000000 +04 +0? +#1350000000000000 +0E$ +0:$ +1.$ +11 +b0 & +b0 -$ +b0 7$ +1' +0=$ +02$ +0O +1V +0)" +10" +0a" +1h" +0;# +1B# +1z# +1Q$ +0O$ +b0 ?$ +b0 . +b0 B$ +1K +1R +1Y +1` +1g +0l +1n +1u +0z +1| +0#" +1%" +1," +13" +1:" +1A" +1H" +1O" +0T" +1V" +0[" +1]" +1d" +1k" +1r" +1y" +0~" +1"# +0'# +1)# +10# +05# +17# +1># +1E# +1L# +1S# +1Z# +0_# +1a# +1h# +0m# +1o# +0t# +b0 # +b0 A +b0 /$ +1v# +1}# +1&$ +18 +b10100010101100101100001011010010 7 +b1010100010101100101100001011010010 " +b1010100010101100101100001011010010 @ +b10100000 H$ +b1 M$ +0J$ +1L$ +b110100000xxxxxxxx ) +b110100000xxxxxxxx A$ +b110100000xxxxxxxx N$ +1@$ +b10 I +b1110 J +b1 F +14 +1? +#1350000000000100 +b10110000 ?$ +b10110000 . +b10110000 B$ +1:$ +b11010000010110000 & +b11010000010110000 -$ +b11010000010110000 7$ +12$ +b10 u# +1t# +b11 n# +1m# +b11 `# +1_# +b1 =# +b11 6# +15# +b11 (# +1'# +b11 !# +1~" +b1 c" +b11 \" +1[" +b11 U" +1T" +b1 +" +b11 $" +1#" +b11 { +1z +b11 m +1l +b110100000101100001100000011010000 # +b110100000101100001100000011010000 A +b110100000101100001100000011010000 /$ +b1 Q +#1351000000000000 +1; +1S$ +#1400000000000000 +04 +0? +#1450000000000000 +0E$ +0.$ +11 +02$ +0:$ +0' +0=$ +0K +1L +0R +1S +0Y +1Z +0` +1a +0g +1h +0l +0n +1o +0u +1v +0z +0| +1} +0#" +0%" +1&" +0," +1-" +03" +14" +0:" +1;" +0A" +1B" +0H" +1I" +0O" +1P" +0T" +0V" +1W" +0[" +0]" +1^" +0d" +1e" +0k" +1l" +0r" +1s" +0y" +1z" +0~" +0"# +1## +0'# +0)# +1*# +00# +11# +05# +07# +18# +0># +1?# +0E# +1F# +0L# +1M# +0S# +1T# +0Z# +1[# +0_# +0a# +1b# +0h# +1i# +0m# +0o# +1p# +0t# +b0 # +b0 A +b0 /$ +0v# +1w# +0}# +1~# +0&$ +1'$ +b0 & +b0 -$ +b0 7$ +b0 ?$ +b0 . +b0 B$ +1G$ +0E +0V +0k +0y +0"" +00" +0S" +0Z" +0h" +0}" +0&# +04# +0B# +0^# +0l# +0z# +b10 F +b1101 J +b11 I +15$ +0@$ +b10 M$ +1+ +b10110000 I$ +b11010000010110000 ) +b11010000010110000 A$ +b11010000010110000 N$ +0= +0D +b0 7 +08 +b0 " +b0 @ +14 +1? +#1450000000000100 +b11000000 ?$ +b11000000 . +b11000000 B$ +b1100000011010000 & +b1100000011010000 -$ +b1100000011010000 7$ +12$ +b10 Q +b1 X +b111 m +1l +b111 { +1z +b111 $" +1#" +b10 +" +b1 2" +b111 U" +1T" +b111 \" +1[" +b10 c" +b1 j" +b111 !# +1~" +b111 (# +1'# +b111 6# +15# +b10 =# +b1 D# +b111 `# +1_# +b111 n# +1m# +b100 u# +1t# +b110100000101100001100000011010000 # +b110100000101100001100000011010000 A +b110100000101100001100000011010000 /$ +b1 |# +#1500000000000000 +04 +0? +#1550000000000000 +13$ +1B +1.$ +1$ +1' +0G$ +0Q$ +b11010000 ?$ +b11010000 . +b11010000 B$ +b1010000010110000 U$ +b1 Z$ +0W$ +1Y$ +b11010000010110000xxxxxxxxxxxxxxxx , +b11010000010110000xxxxxxxxxxxxxxxx R$ +b11000000 H$ +b1 M$ +0+ +0L$ +b1100000010110000 ) +b1100000010110000 A$ +b1100000010110000 N$ +1@$ +14 +1? +#1600000000000000 +04 +0? +#1650000000000000 +0E$ +11 +0=$ +03$ +0B +0.$ +02$ +0:$ +0$ +0' +1K +1P +0L +1R +0S +0W +1Y +0Z +1` +0a +1g +0h +1n +0o +1u +0v +1| +0} +1%" +1*" +0&" +1," +0-" +01" +13" +04" +1:" +0;" +1A" +0B" +1H" +0I" +1O" +0P" +1V" +0W" +1]" +1b" +0^" +1d" +0e" +0i" +1k" +0l" +1r" +0s" +1y" +0z" +1"# +0## +1)# +0*# +10# +01# +17# +1<# +08# +1># +0?# +0C# +1E# +0F# +1L# +0M# +1S# +0T# +1Z# +0[# +1a# +0b# +1h# +0i# +1o# +0p# +0t# +1v# +0w# +0{# +b10100001101100011100000111010001 # +b10100001101100011100000111010001 A +b10100001101100011100000111010001 /$ +1}# +0~# +1&$ +0'$ +b1010000110110001 & +b1010000110110001 -$ +b1010000110110001 7$ +b10100001 ?$ +b10100001 . +b10100001 B$ +1G$ +b1 F +b1110 J +b10 I +05$ +0@$ +b10 M$ +1+ +b11010000 I$ +b1100000011010000 ) +b1100000011010000 A$ +b1100000011010000 N$ +14 +1? +#1700000000000000 +04 +0? +#1750000000000000 +1.$ +1' +1T$ +0G$ +b10110001 ?$ +b10110001 . +b10110001 B$ +b1100000011010000 V$ +b110100000101100001100000011010000 , +b110100000101100001100000011010000 R$ +b10 Z$ +1- +b10100001 H$ +b1010000111010000 ) +b1010000111010000 A$ +b1010000111010000 N$ +b1 M$ +0+ +1@$ +14 +1? +#1800000000000000 +04 +0? +#1850000000000000 +0.$ +0' +b1100000111010001 & +b1100000111010001 -$ +b1100000111010001 7$ +b11000001 ?$ +b11000001 . +b11000001 B$ +1G$ +0T$ +15$ +0@$ +b10 M$ +1+ +b10110001 I$ +b1010000110110001 ) +b1010000110110001 A$ +b1010000110110001 N$ +b0 Z$ +0- +14 +1? +#1900000000000000 +04 +0? +#1950000000000000 +13$ +1B +1.$ +1$ +1' +0G$ +b11010001 ?$ +b11010001 . +b11010001 B$ +b1010000110110001 U$ +b1 Z$ +0Y$ +b10100001101100011100000011010000 , +b10100001101100011100000011010000 R$ +b11000001 H$ +b1100000110110001 ) +b1100000110110001 A$ +b1100000110110001 N$ +b1 M$ +0+ +1@$ +14 +1? +#2000000000000000 +04 +0? +#2050000000000000 +03$ +0B +0.$ +10$ +0$ +0' +0K +0P +0R +1W +0Y +0` +0g +0n +0u +0| +0%" +0*" +0," +11" +03" +0:" +0A" +0H" +0O" +0V" +0]" +0b" +0d" +1i" +0k" +0r" +0y" +0"# +0)# +00# +07# +0<# +0># +1C# +0E# +0L# +0S# +0Z# +0a# +0h# +0o# +0v# +1{# +b1010100010101100101100001011010010 # +b1010100010101100101100001011010010 A +b1010100010101100101100001011010010 /$ +0}# +0&$ +b1010001010110010 & +b1010001010110010 -$ +b1010001010110010 7$ +b10100010 ?$ +b10100010 . +b10100010 B$ +1G$ +b0 F +b1111 J +b1 I +05$ +0@$ +b10 M$ +1+ +b11010001 I$ +b1100000111010001 ) +b1100000111010001 A$ +b1100000111010001 N$ +14 +1? +#2100000000000000 +04 +0? +#2150000000000000 +1.$ +1' +1T$ +0G$ +b10110010 ?$ +b10110010 . +b10110010 B$ +b1100000111010001 V$ +b10100001101100011100000111010001 , +b10100001101100011100000111010001 R$ +b10 Z$ +1- +b10100010 H$ +b1010001011010001 ) +b1010001011010001 A$ +b1010001011010001 N$ +b1 M$ +0+ +1@$ +14 +1? +#2200000000000000 +04 +0? +#2250000000000000 +0.$ +18$ +0' +b101100001011010010 & +b101100001011010010 -$ +b101100001011010010 7$ +b11000010 ?$ +b11000010 . +b11000010 B$ +1G$ +0T$ +15$ +0@$ +b10 M$ +1+ +b10110010 I$ +b1010001010110010 ) +b1010001010110010 A$ +b1010001010110010 N$ +b0 Z$ +0- +14 +1? +#2300000000000000 +04 +0? +#2350000000000000 +1D$ +13$ +1B +00 +1.$ +1$ +1<$ +1' +0G$ +b11010010 ?$ +b11010010 . +b11010010 B$ +b1010001010110010 U$ +b10100010101100101100000111010001 , +b10100010101100101100000111010001 R$ +b1 Z$ +b11000010 H$ +b1100001010110010 ) +b1100001010110010 A$ +b1100001010110010 N$ +b1 M$ +0+ +1@$ +14 +1? +#2400000000000000 +04 +0? +#2450000000000000 +0D$ +0' +0F$ +10 +0.$ +06$ +12 +03$ +0B +08$ +0$ +0<$ +0>$ +0( +0% +b1010001010110010 & +b1010001010110010 -$ +b1010001010110010 7$ +b10100010 ?$ +b10100010 . +b10100010 B$ +1G$ +1O$ +1G +b10000 J +b0 I +05$ +0@$ +1J$ +b10 M$ +1+ +b11010010 I$ +b101100001011010010 ) +b101100001011010010 A$ +b101100001011010010 N$ +14 +1? +#2500000000000000 +04 +0? +#2550000000000000 +1T$ +0G$ +b1100001011010010 V$ +b10 Z$ +1- +1W$ +b1010100010101100101100001011010010 , +b1010100010101100101100001011010010 R$ +b0 M$ +0+ +14 +1? +#2600000000000000 +04 +0? +#2650000000000000 +0T$ +b0 Z$ +0- +14 +1? +#2700000000000000 +04 +0? +#2750000000000000 +14 +1? +#2800000000000000 +04 +0? +#2850000000000000 +14 +1? +#2900000000000000 +04 +0? +#2950000000000000 +14 +1? +#3000000000000000 +04 +0? +#3050000000000000 +14 +1? +#3100000000000000 +04 +0? +#3150000000000000 +14 +1? +#3200000000000000 +04 +0? +#3250000000000000 +14 +1? +#3300000000000000 +04 +0? +#3350000000000000 +14 +1? +#3400000000000000 +04 +0? +#3450000000000000 +14 +1? +#3500000000000000 +04 +0? +#3550000000000000 +14 +1? +#3600000000000000 +04 +0? +#3650000000000000 +14 +1? +#3700000000000000 +04 +0? +#3750000000000000 +14 +1? +#3800000000000000 +04 +0? +#3850000000000000 +14 +1? +#3900000000000000 +04 +0? +#3950000000000000 +14 +1? +#4000000000000000 +04 +0? +#4050000000000000 +14 +1? +#4100000000000000 +04 +0? +#4150000000000000 +14 +1? +#4200000000000000 +04 +0? +#4250000000000000 +14 +1? +#4300000000000000 +04 +0? +#4350000000000000 +14 +1? +#4400000000000000 +04 +0? +#4450000000000000 +14 +1? +#4500000000000000 +04 +0? +#4550000000000000 +14 +1? +#4600000000000000 +04 +0? +#4650000000000000 +14 +1? +#4700000000000000 +04 +0? +#4750000000000000 +14 +1? +#4800000000000000 +04 +0? +#4850000000000000 +14 +1? +#4900000000000000 +04 +0? +#4950000000000000 +14 +1? +#5000000000000000 +04 +0? +#5050000000000000 +14 +1? +#5100000000000000 +04 +0? +#5150000000000000 +14 +1? +#5200000000000000 +04 +0? +#5250000000000000 +14 +1? +#5300000000000000 +04 +0? +#5350000000000000 +14 +1? +#5400000000000000 +04 +0? +#5450000000000000 +14 +1? +#5500000000000000 +04 +0? +#5550000000000000 +14 +1? +#5600000000000000 +04 +0? +#5650000000000000 +14 +1? +#5700000000000000 +04 +0? +#5750000000000000 +14 +1? +#5800000000000000 +04 +0? +#5850000000000000 +14 +1? +#5900000000000000 +04 +0? +#5950000000000000 +14 +1? +#6000000000000000 +04 +0? +#6050000000000000 +14 +1? +#6100000000000000 +04 +0? +#6150000000000000 +14 +1? +#6200000000000000 +04 +0? +#6250000000000000 +14 +1? +#6300000000000000 +04 +0? +#6350000000000000 +14 +1? +#6400000000000000 +04 +0? +#6450000000000000 +14 +1? +#6500000000000000 +04 +0? +#6550000000000000 +14 +1? +#6600000000000000 +04 +0? +#6650000000000000 +14 +1? +#6700000000000000 +04 +0? +#6750000000000000 +14 +1? +#6800000000000000 +04 +0? +#6850000000000000 +14 +1? +#6900000000000000 +04 +0? +#6950000000000000 +14 +1? +#7000000000000000 +04 +0? +#7050000000000000 +14 +1? +#7100000000000000 +04 +0? +#7150000000000000 +14 +1? +#7200000000000000 +04 +0? +#7250000000000000 +14 +1? +#7300000000000000 +04 +0? +#7350000000000000 +14 +1? +#7400000000000000 +04 +0? +#7450000000000000 +14 +1? +#7500000000000000 +04 +0? +#7550000000000000 +14 +1? +#7600000000000000 +04 +0? +#7650000000000000 +14 +1? +#7700000000000000 +04 +0? +#7750000000000000 +14 +1? +#7800000000000000 +04 +0? +#7850000000000000 +14 +1? +#7900000000000000 +04 +0? +#7950000000000000 +14 +1? +#8000000000000000 +04 +0? +#8050000000000000 +14 +1? +#8100000000000000 +04 +0? +#8150000000000000 +14 +1? +#8200000000000000 +04 +0? +#8250000000000000 +14 +1? +#8300000000000000 +04 +0? +#8350000000000000 +14 +1? +#8400000000000000 +04 +0? +#8450000000000000 +14 +1? +#8500000000000000 +04 +0? +#8550000000000000 +14 +1? +#8600000000000000 +04 +0? +#8650000000000000 +14 +1? +#8700000000000000 +04 +0? +#8750000000000000 +14 +1? +#8800000000000000 +04 +0? +#8850000000000000 +14 +1? +#8900000000000000 +04 +0? +#8950000000000000 +14 +1? +#9000000000000000 +04 +0? +#9050000000000000 +14 +1? +#9100000000000000 +04 +0? +#9150000000000000 +14 +1? +#9200000000000000 +04 +0? +#9250000000000000 +14 +1? +#9300000000000000 +04 +0? +#9350000000000000 +14 +1? +#9400000000000000 +04 +0? +#9450000000000000 +14 +1? +#9500000000000000 +04 +0? +#9550000000000000 +14 +1? +#9600000000000000 +04 +0? +#9650000000000000 +14 +1? +#9700000000000000 +04 +0? +#9750000000000000 +14 +1? +#9800000000000000 +04 +0? +#9850000000000000 +14 +1? +#9900000000000000 +04 +0? +#9950000000000000 +14 +1? +#10000000000000000 +04 +0? +#10050000000000000 +14 +1? +#10100000000000000 +04 +0? +#10150000000000000 +14 +1? +#10200000000000000 +04 +0? +#10250000000000000 +14 +1? +#10300000000000000 +04 +0? +#10350000000000000 +14 +1? +#10400000000000000 +04 +0? +#10450000000000000 +14 +1? +#10500000000000000 +04 +0? +#10550000000000000 +14 +1? +#10600000000000000 +04 +0? +#10650000000000000 +14 +1? +#10700000000000000 +04 +0? +#10750000000000000 +14 +1? +#10800000000000000 +04 +0? +#10850000000000000 +14 +1? +#10900000000000000 +04 +0? +#10950000000000000 +14 +1? +#11000000000000000 +04 +0? +#11050000000000000 +14 +1? +#11100000000000000 +04 +0? +#11150000000000000 +14 +1? +#11200000000000000 +04 +0? +#11250000000000000 +14 +1? +#11300000000000000 +04 +0? +#11350000000000000 +14 +1? +#11400000000000000 +04 +0? +#11450000000000000 +14 +1? +#11500000000000000 +04 +0? +#11550000000000000 +14 +1? +#11600000000000000 +04 +0? +#11650000000000000 +1k +1r +1"" +1L" +1Z" +1}" +1&# +1-# +14# +1^# +1e# +1l# +1s# +1E +1: +b11100000111100001010000010110000 7 +b111100000111100001010000010110000 " +b111100000111100001010000010110000 @ +1= +1D +b100 5 +b100100 [$ +b11100000111100001010000010110000 \$ +14 +1? +#11700000000000000 +04 +0? +#11750000000000000 +1F$ +16$ +02 +1>$ +1( +1% +1O +1)" +1a" +1;# +0s# +b1 I +b1111 J +0G +b1000 5 +b11100001111100011010000110110001 7 +0: +b11100001111100011010000110110001 " +b11100001111100011010000110110001 @ +14 +1? +#11750000000000100 +1E$ +01 +1=$ +b11100000 ?$ +b11100000 . +b11100000 B$ +1:$ +b11110000011110000 & +b11110000011110000 -$ +b11110000011110000 7$ +12$ +00$ +b10 |# +0{# +b1001 u# +1t# +b1111 n# +b1 g# +1f# +b1111 `# +b10 D# +0C# +b100 =# +b1111 6# +b1 /# +1.# +b1111 (# +b1111 !# +b10 j" +0i" +b100 c" +b1111 \" +b1110 U" +0T" +b1 N" +1M" +b10 2" +01" +b100 +" +b1111 $" +b1110 { +0z +b1 t +1s +b1111 m +b10 X +0W +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +b100 Q +#11800000000000000 +04 +0? +#11850000000000000 +0:$ +0E$ +b1010001010110010 & +b1010001010110010 -$ +b1010001010110010 7$ +1.$ +11 +02$ +10$ +1' +0=$ +0O +1V +0)" +10" +0a" +1h" +0;# +1B# +1K +1R +1W +1Y +1` +1g +1n +0s +1u +1z +1| +1%" +1," +11" +13" +1:" +1A" +1H" +0M" +1O" +1T" +1V" +1]" +1d" +1i" +1k" +1r" +1y" +1"# +1)# +0.# +10# +17# +1># +1C# +1E# +1L# +1S# +1Z# +1a# +0f# +1h# +1o# +0t# +1v# +1{# +b1010100010101100101100001011010010 # +b1010100010101100101100001011010010 A +b1010100010101100101100001011010010 /$ +1}# +1&$ +b10110010 ?$ +b10110010 . +b10110010 B$ +1Q$ +0O$ +b1100 5 +b11100010111100101010001010110010 7 +b11100010111100101010001010110010 " +b11100010111100101010001010110010 @ +b1 F +b1110 J +b10 I +1@$ +1L$ +0J$ +b1 M$ +b11100000 H$ +b11110000011010010 ) +b11110000011010010 A$ +b11110000011010010 N$ +14 +1? +#11850000000000100 +b11110000 ?$ +b11110000 . +b11110000 B$ +1:$ +b11110000011110000 & +b11110000011110000 -$ +b11110000011110000 7$ +12$ +00$ +b1001 Q +b100 X +0W +b11111 m +b11 t +1s +b11100 { +0z +b11111 $" +b1001 +" +b100 2" +01" +b11 N" +1M" +b11100 U" +0T" +b11111 \" +b1001 c" +b100 j" +0i" +b11111 !# +b11111 (# +b11 /# +1.# +b11111 6# +b1001 =# +b100 D# +0C# +b11111 `# +b11 g# +1f# +b11111 n# +b10010 u# +1t# +b100 |# +0{# +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +#11900000000000000 +04 +0? +#11950000000000000 +18$ +0.$ +03$ +0B +0' +0:$ +0$ +02$ +10$ +1G$ +b11000010 ?$ +b11000010 . +b11000010 B$ +b101100001011010010 & +b101100001011010010 -$ +b101100001011010010 7$ +0K +1L +0P +0R +1W +1S +0Y +1Z +0` +1a +0g +1h +0n +1o +0s +0u +1v +1z +0| +1} +0%" +1&" +0*" +0," +11" +1-" +03" +14" +0:" +1;" +0A" +1B" +0H" +1I" +0M" +0O" +1P" +1T" +0V" +1W" +0]" +1^" +0b" +0d" +1i" +1e" +0k" +1l" +0r" +1s" +0y" +1z" +0"# +1## +0)# +1*# +0.# +00# +11# +07# +18# +0<# +0># +1C# +1?# +0E# +1F# +0L# +1M# +0S# +1T# +0Z# +1[# +0a# +1b# +0f# +0h# +1i# +0o# +1p# +0t# +0v# +1{# +b1010100010101100101100001011010010 # +b1010100010101100101100001011010010 A +b1010100010101100101100001011010010 /$ +1w# +0}# +1~# +0&$ +1'$ +1O +1)" +1a" +1;# +b11110000 I$ +b11110000011110000 ) +b11110000011110000 A$ +b11110000011110000 N$ +b10 M$ +1+ +0@$ +15$ +b11 I +b1101 J +b10 F +b10000 5 +b11100011111100111010001110110011 7 +b11100011111100111010001110110011 " +b11100011111100111010001110110011 @ +14 +1? +#11950000000000100 +b10100000 ?$ +b10100000 . +b10100000 B$ +08$ +b1010000010110000 & +b1010000010110000 -$ +b1010000010110000 7$ +12$ +00$ +b1000 |# +0{# +b100100 u# +1t# +b111111 n# +b111 g# +1f# +b111111 `# +b1001 D# +0C# +b10010 =# +b111111 6# +b111 /# +1.# +b111111 (# +b111111 !# +b1001 j" +0i" +b10010 c" +b111111 \" +b111000 U" +0T" +b111 N" +1M" +b1001 2" +01" +b10010 +" +b111111 $" +b111000 { +0z +b111 t +1s +b111111 m +b1001 X +0W +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +b10010 Q +#12000000000000000 +04 +0? +#12050000000000000 +1D$ +00 +1<$ +18$ +13$ +1B +b101100001011010010 & +b101100001011010010 -$ +b101100001011010010 7$ +1.$ +1$ +02$ +10$ +1' +0O +0V +1] +0)" +00" +17" +0a" +0h" +1o" +0;# +0B# +1I# +1K +1R +1W +1Y +1` +1g +1n +0s +1u +1z +1| +1%" +1," +11" +13" +1:" +1A" +1H" +0M" +1O" +1T" +1V" +1]" +1d" +1i" +1k" +1r" +1y" +1"# +1)# +0.# +10# +17# +1># +1C# +1E# +1L# +1S# +1Z# +1a# +0f# +1h# +1o# +0t# +1v# +1{# +b1010100010101100101100001011010010 # +b1010100010101100101100001011010010 A +b1010100010101100101100001011010010 /$ +1}# +1&$ +b11010010 ?$ +b11010010 . +b11010010 B$ +0G$ +0Q$ +b10100 5 +b11100100111101001010010010110100 7 +b11100100111101001010010010110100 " +b11100100111101001010010010110100 @ +b11 F +b1100 J +b100 I +1@$ +0L$ +b1 M$ +0+ +b10100000 H$ +b1010000011110000 ) +b1010000011110000 A$ +b1010000011110000 N$ +1Y$ +0W$ +b1 Z$ +b1110000011110000 U$ +b111100000111100001100001011010010 , +b111100000111100001100001011010010 R$ +14 +1? +#12050000000000100 +0D$ +10 +0<$ +b10110000 ?$ +b10110000 . +b10110000 B$ +08$ +b1010000010110000 & +b1010000010110000 -$ +b1010000010110000 7$ +12$ +00$ +b100101 Q +b10011 X +0W +b1111111 m +b1111 t +1s +b1110000 { +0z +b1111111 $" +b100101 +" +b10011 2" +01" +b1111 N" +1M" +b1110000 U" +0T" +b1111111 \" +b100101 c" +b10011 j" +0i" +b1111111 !# +b1111111 (# +b1111 /# +1.# +b1111111 6# +b100101 =# +b10011 D# +0C# +b1111111 `# +b1111 g# +1f# +b1111111 n# +b1001000 u# +1t# +b10000 |# +0{# +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +#12100000000000000 +04 +0? +#12150000000000000 +1E$ +0.$ +01 +03$ +0B +0' +1=$ +1:$ +0$ +1G$ +b11100000 ?$ +b11100000 . +b11100000 B$ +b11110000011110000 & +b11110000011110000 -$ +b11110000011110000 7$ +1O +1)" +1a" +1;# +b10110000 I$ +b1010000010110000 ) +b1010000010110000 A$ +b1010000010110000 N$ +b10 M$ +1+ +0@$ +05$ +b11000 5 +b11100101111101011010010110110101 7 +b11100101111101011010010110110101 " +b11100101111101011010010110110101 @ +14 +1? +#12150000000000100 +0E$ +11 +0=$ +b11100001 ?$ +b11100001 . +b11100001 B$ +0:$ +b1110000111110001 & +b1110000111110001 -$ +b1110000111110001 7$ +02$ +b100000 |# +b10010000 u# +0t# +b11111111 n# +b11111 g# +b11111111 `# +b1 K# +b100110 D# +b1001010 =# +1<# +b11111111 6# +b11111 /# +b11111111 (# +b11111111 !# +b1 q" +b100110 j" +b1001010 c" +1b" +b11111111 \" +b11100000 U" +b11111 N" +b1 9" +b100110 2" +b1001010 +" +1*" +b11111111 $" +b11100000 { +b11111 t +b11111111 m +b1 _ +b100110 X +b1001010 Q +1P +b11100001111100011010000110110001 # +b11100001111100011010000110110001 A +b11100001111100011010000110110001 /$ +#12200000000000000 +04 +0? +#12250000000000000 +1:$ +b11110000011110000 & +b11110000011110000 -$ +b11110000011110000 7$ +1.$ +12$ +1' +0O +1V +0)" +10" +0a" +1h" +0;# +1B# +0K +0L +1M +0P +0R +0S +0W +1T +0Y +0Z +1[ +0` +0a +1b +0g +0h +1i +0n +0o +1p +1s +0u +0v +1w +0z +0| +0} +1~ +0%" +0&" +1'" +0*" +0," +0-" +01" +1." +03" +04" +15" +0:" +0;" +1<" +0A" +0B" +1C" +0H" +0I" +1J" +1M" +0O" +0P" +1Q" +0T" +0V" +0W" +1X" +0]" +0^" +1_" +0b" +0d" +0e" +0i" +1f" +0k" +0l" +1m" +0r" +0s" +1t" +0y" +0z" +1{" +0"# +0## +1$# +0)# +0*# +1+# +1.# +00# +01# +12# +07# +08# +19# +0<# +0># +0?# +0C# +1@# +0E# +0F# +1G# +0L# +0M# +1N# +0S# +0T# +1U# +0Z# +0[# +1\# +0a# +0b# +1c# +1f# +0h# +0i# +1j# +0o# +0p# +1q# +1t# +0v# +0w# +0{# +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +1x# +0}# +0~# +1!$ +0&$ +0'$ +1($ +b11110000 ?$ +b11110000 . +b11110000 B$ +0G$ +1T$ +b11100 5 +b11100110111101101010011010110110 7 +b11100110111101101010011010110110 " +b11100110111101101010011010110110 @ +b100 F +b1011 J +b101 I +1@$ +b1 M$ +0+ +b11100001 H$ +b1110000110110000 ) +b1110000110110000 A$ +b1110000110110000 N$ +b10 Z$ +1- +b1010000010110000 V$ +b111100000111100001010000010110000 , +b111100000111100001010000010110000 R$ +14 +1? +#12250000000000100 +b11110001 ?$ +b11110001 . +b11110001 B$ +0:$ +b1110000111110001 & +b1110000111110001 -$ +b1110000111110001 7$ +02$ +b10010101 Q +1P +b1001100 X +b11 _ +b111111111 m +b111111 t +b111000000 { +b111111111 $" +b10010101 +" +1*" +b1001100 2" +b11 9" +b111111 N" +b111000000 U" +b111111111 \" +b10010101 c" +1b" +b1001100 j" +b11 q" +b111111111 !# +b111111111 (# +b111111 /# +b111111111 6# +b10010101 =# +1<# +b1001100 D# +b11 K# +b111111111 `# +b111111 g# +b111111111 n# +b100100000 u# +0t# +b11100001111100011010000110110001 # +b11100001111100011010000110110001 A +b11100001111100011010000110110001 /$ +b1000000 |# +#12300000000000000 +04 +0? +#12350000000000000 +0.$ +03$ +0B +0' +0$ +12$ +0T$ +1G$ +b10100000 ?$ +b10100000 . +b10100000 B$ +b1010000010110000 & +b1010000010110000 -$ +b1010000010110000 7$ +1K +0P +1R +1Y +1` +1g +1n +1u +1| +1%" +0*" +1," +13" +1:" +1A" +1H" +1O" +1V" +1]" +0b" +1d" +1k" +1r" +1y" +1"# +1)# +10# +17# +0<# +1># +1E# +1L# +1S# +1Z# +1a# +1h# +1o# +1t# +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +1v# +1}# +1&$ +1O +1)" +1a" +1;# +b0 Z$ +0- +b11110001 I$ +b1110000111110001 ) +b1110000111110001 A$ +b1110000111110001 N$ +b10 M$ +1+ +0@$ +15$ +b110 I +b1010 J +b101 F +b100000 5 +b11100111111101111010011110110111 7 +b11100111111101111010011110110111 " +b11100111111101111010011110110111 @ +14 +1? +#12350000000000100 +b10100001 ?$ +b10100001 . +b10100001 B$ +b1010000110110001 & +b1010000110110001 -$ +b1010000110110001 7$ +02$ +b10000000 |# +b1001000000 u# +0t# +b1111111111 n# +b1111111 g# +b1111111111 `# +b111 K# +b10011001 D# +b100101010 =# +1<# +b1111111111 6# +b1111111 /# +b1111111111 (# +b1111111111 !# +b111 q" +b10011001 j" +b100101010 c" +1b" +b1111111111 \" +b1110000000 U" +b1111111 N" +b111 9" +b10011001 2" +b100101010 +" +1*" +b1111111111 $" +b1110000000 { +b1111111 t +b1111111111 m +b111 _ +b10011001 X +b100101010 Q +1P +b11100001111100011010000110110001 # +b11100001111100011010000110110001 A +b11100001111100011010000110110001 /$ +#12400000000000000 +04 +0? +#12450000000000000 +13$ +1B +b1010000010110000 & +b1010000010110000 -$ +b1010000010110000 7$ +1.$ +1$ +12$ +1' +0O +0V +0] +1d +0)" +00" +07" +1>" +0a" +0h" +0o" +1v" +0;# +0B# +0I# +1P# +1z# +0K +1L +0P +0R +1S +0W +0Y +1Z +0` +1a +0g +1h +0n +1o +1s +0u +1v +0z +0| +1} +0%" +1&" +0*" +0," +1-" +01" +03" +14" +0:" +1;" +0A" +1B" +0H" +1I" +1M" +0O" +1P" +0T" +0V" +1W" +0]" +1^" +0b" +0d" +1e" +0i" +0k" +1l" +0r" +1s" +0y" +1z" +0"# +1## +0)# +1*# +1.# +00# +11# +07# +18# +0<# +0># +1?# +0C# +0E# +1F# +0L# +1M# +0S# +1T# +0Z# +1[# +0a# +1b# +1f# +0h# +1i# +0o# +1t# +1p# +0v# +1w# +0{# +b111100000111100001010000010110000 # +b111100000111100001010000010110000 A +b111100000111100001010000010110000 /$ +0}# +1~# +0&$ +1'$ +b10110000 ?$ +b10110000 . +b10110000 B$ +0G$ +18 +b11101000111110001010100010111000 7 +b1011101000111110001010100010111000 " +b1011101000111110001010100010111000 @ +b110 F +b1001 J +b111 I +1@$ +b1 M$ +0+ +b10100001 H$ +b1010000111110001 ) +b1010000111110001 A$ +b1010000111110001 N$ +0Y$ +b1 Z$ +b1110000111110001 U$ +b11100001111100011010000010110000 , +b11100001111100011010000010110000 R$ +14 +1? +#12450000000000100 +b10110001 ?$ +b10110001 . +b10110001 B$ +b1010000110110001 & +b1010000110110001 -$ +b1010000110110001 7$ +02$ +b1001010101 Q +1P +b100110011 X +b1111 _ +b11111111111 m +b11111111 t +b11100000000 { +b11111111111 $" +b1001010101 +" +1*" +b100110011 2" +b1111 9" +b11111111 N" +b11100000000 U" +b11111111111 \" +b1001010101 c" +1b" +b100110011 j" +b1111 q" +b11111111111 !# +b11111111111 (# +b11111111 /# +b11111111111 6# +b1001010101 =# +1<# +b100110011 D# +b1111 K# +b11111111111 `# +b11111111 g# +b11111111111 n# +b10010000000 u# +0t# +b11100001111100011010000110110001 # +b11100001111100011010000110110001 A +b11100001111100011010000110110001 /$ +b100000000 |# +#12500000000000000 +04 +0? +#12550000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100001 ?$ +b11100001 . +b11100001 B$ +b1110000111110001 & +b1110000111110001 -$ +b1110000111110001 7$ +0E +0d +0k +0r +0"" +0>" +0L" +0Z" +0v" +0}" +0&# +0-# +04# +0P# +0^# +0e# +0l# +0z# +b10110001 I$ +b1010000110110001 ) +b1010000110110001 A$ +b1010000110110001 N$ +b10 M$ +1+ +0@$ +05$ +0= +0D +b0 7 +08 +b0 " +b0 @ +14 +1? +#12550000000000100 +b11100010 ?$ +b11100010 . +b11100010 B$ +b1110001011110010 & +b1110001011110010 -$ +b1110001011110010 7$ +b1000000001 |# +b100100000000 u# +b111111111111 n# +b111111111 g# +b111111111111 `# +b1 R# +b11110 K# +b1001100110 D# +1C# +b10010101010 =# +0<# +b111111111111 6# +b111111111 /# +b111111111111 (# +b111111111111 !# +b1 x" +b11110 q" +b1001100110 j" +1i" +b10010101010 c" +0b" +b111111111111 \" +b111000000000 U" +b111111111 N" +b1 @" +b11110 9" +b1001100110 2" +11" +b10010101010 +" +0*" +b111111111111 $" +b111000000000 { +b111111111 t +b111111111111 m +b1 f +b11110 _ +b1001100110 X +1W +b10010101010 Q +0P +b11100010111100101010001010110010 # +b11100010111100101010001010110010 A +b11100010111100101010001010110010 /$ +#12600000000000000 +04 +0? +#12650000000000000 +1.$ +1' +b11110010 ?$ +b11110010 . +b11110010 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100010 H$ +b1110001010110001 ) +b1110001010110001 A$ +b1110001010110001 N$ +b10 Z$ +1- +b1010000110110001 V$ +b11100001111100011010000110110001 , +b11100001111100011010000110110001 R$ +14 +1? +#12700000000000000 +04 +0? +#12750000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100010 ?$ +b10100010 . +b10100010 B$ +b1010001010110010 & +b1010001010110010 -$ +b1010001010110010 7$ +b0 Z$ +0- +b11110010 I$ +b1110001011110010 ) +b1110001011110010 A$ +b1110001011110010 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#12800000000000000 +04 +0? +#12850000000000000 +13$ +1B +1.$ +1$ +1' +b10110010 ?$ +b10110010 . +b10110010 B$ +0G$ +1@$ +b1 M$ +0+ +b10100010 H$ +b1010001011110010 ) +b1010001011110010 A$ +b1010001011110010 N$ +b1 Z$ +b1110001011110010 U$ +b11100010111100101010000110110001 , +b11100010111100101010000110110001 R$ +14 +1? +#12900000000000000 +04 +0? +#12950000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100011 ?$ +b11100011 . +b11100011 B$ +b1110001111110011 & +b1110001111110011 -$ +b1110001111110011 7$ +1K +1P +0L +1R +0S +1W +1Y +0Z +0^ +1` +0a +1g +0h +1n +0o +1u +0v +1| +0} +1%" +1*" +0&" +1," +0-" +11" +13" +04" +08" +1:" +0;" +1A" +0B" +1H" +0I" +1O" +0P" +1V" +0W" +1]" +1b" +0^" +1d" +0e" +1i" +1k" +0l" +0p" +1r" +0s" +1y" +0z" +1"# +0## +1)# +0*# +10# +01# +17# +1<# +08# +1># +0?# +1C# +1E# +0F# +0J# +b11100011111100111010001110110011 # +b11100011111100111010001110110011 A +b11100011111100111010001110110011 /$ +1L# +0M# +1S# +0T# +1Z# +0[# +1a# +0b# +1h# +0i# +1o# +0p# +1v# +0w# +1}# +0~# +1&$ +0'$ +b10110010 I$ +b1010001010110010 ) +b1010001010110010 A$ +b1010001010110010 N$ +b10 M$ +1+ +0@$ +05$ +b110 I +b1010 J +b101 F +14 +1? +#13000000000000000 +04 +0? +#13050000000000000 +1.$ +1' +b11110011 ?$ +b11110011 . +b11110011 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100011 H$ +b1110001110110010 ) +b1110001110110010 A$ +b1110001110110010 N$ +b10 Z$ +1- +b1010001010110010 V$ +b11100010111100101010001010110010 , +b11100010111100101010001010110010 R$ +14 +1? +#13100000000000000 +04 +0? +#13150000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100011 ?$ +b10100011 . +b10100011 B$ +b1010001110110011 & +b1010001110110011 -$ +b1010001110110011 7$ +b0 Z$ +0- +b11110011 I$ +b1110001111110011 ) +b1110001111110011 A$ +b1110001111110011 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#13200000000000000 +04 +0? +#13250000000000000 +13$ +1B +1.$ +1$ +1' +b10110011 ?$ +b10110011 . +b10110011 B$ +0G$ +1@$ +b1 M$ +0+ +b10100011 H$ +b1010001111110011 ) +b1010001111110011 A$ +b1010001111110011 N$ +b1 Z$ +b1110001111110011 U$ +b11100011111100111010001010110010 , +b11100011111100111010001010110010 R$ +14 +1? +#13300000000000000 +04 +0? +#13350000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100100 ?$ +b11100100 . +b11100100 B$ +b1110010011110100 & +b1110010011110100 -$ +b1110010011110100 7$ +0K +0P +0R +0W +0Y +1^ +0` +0g +0n +0u +0| +0%" +0*" +0," +01" +03" +18" +0:" +0A" +0H" +0O" +0V" +0]" +0b" +0d" +0i" +0k" +1p" +0r" +0y" +0"# +0)# +00# +07# +0<# +0># +0C# +0E# +1J# +b11100100111101001010010010110100 # +b11100100111101001010010010110100 A +b11100100111101001010010010110100 /$ +0L# +0S# +0Z# +0a# +0h# +0o# +0v# +0}# +0&$ +b10110011 I$ +b1010001110110011 ) +b1010001110110011 A$ +b1010001110110011 N$ +b10 M$ +1+ +0@$ +05$ +b101 I +b1011 J +b100 F +14 +1? +#13400000000000000 +04 +0? +#13450000000000000 +1.$ +1' +b11110100 ?$ +b11110100 . +b11110100 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100100 H$ +b1110010010110011 ) +b1110010010110011 A$ +b1110010010110011 N$ +b10 Z$ +1- +b1010001110110011 V$ +b11100011111100111010001110110011 , +b11100011111100111010001110110011 R$ +14 +1? +#13500000000000000 +04 +0? +#13550000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100100 ?$ +b10100100 . +b10100100 B$ +b1010010010110100 & +b1010010010110100 -$ +b1010010010110100 7$ +b0 Z$ +0- +b11110100 I$ +b1110010011110100 ) +b1110010011110100 A$ +b1110010011110100 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#13600000000000000 +04 +0? +#13650000000000000 +13$ +1B +1.$ +1$ +1' +b10110100 ?$ +b10110100 . +b10110100 B$ +0G$ +1@$ +b1 M$ +0+ +b10100100 H$ +b1010010011110100 ) +b1010010011110100 A$ +b1010010011110100 N$ +b1 Z$ +b1110010011110100 U$ +b11100100111101001010001110110011 , +b11100100111101001010001110110011 R$ +14 +1? +#13700000000000000 +04 +0? +#13750000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100101 ?$ +b11100101 . +b11100101 B$ +b1110010111110101 & +b1110010111110101 -$ +b1110010111110101 7$ +1K +1P +1L +0M +1R +1S +0W +0T +1Y +1Z +0[ +1^ +1` +1a +0b +0e +1g +1h +0i +1n +1o +0p +1u +1v +0w +1| +1} +0~ +1%" +1*" +1&" +0'" +1," +1-" +01" +0." +13" +14" +05" +18" +1:" +1;" +0<" +0?" +1A" +1B" +0C" +1H" +1I" +0J" +1O" +1P" +0Q" +1V" +1W" +0X" +1]" +1b" +1^" +0_" +1d" +1e" +0i" +0f" +1k" +1l" +0m" +1p" +1r" +1s" +0t" +0w" +1y" +1z" +0{" +1"# +1## +0$# +1)# +1*# +0+# +10# +11# +02# +17# +1<# +18# +09# +1># +1?# +0C# +0@# +1E# +1F# +0G# +1J# +1L# +1M# +0N# +0Q# +1S# +1T# +0U# +1Z# +1[# +0\# +1a# +1b# +0c# +1h# +1i# +0j# +1o# +1p# +0q# +1v# +1w# +0x# +0{# +b11100101111101011010010110110101 # +b11100101111101011010010110110101 A +b11100101111101011010010110110101 /$ +1}# +1~# +0!$ +1&$ +1'$ +0($ +b10110100 I$ +b1010010010110100 ) +b1010010010110100 A$ +b1010010010110100 N$ +b10 M$ +1+ +0@$ +05$ +b100 I +b1100 J +b11 F +14 +1? +#13800000000000000 +04 +0? +#13850000000000000 +1.$ +1' +b11110101 ?$ +b11110101 . +b11110101 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100101 H$ +b1110010110110100 ) +b1110010110110100 A$ +b1110010110110100 N$ +b10 Z$ +1- +b1010010010110100 V$ +b11100100111101001010010010110100 , +b11100100111101001010010010110100 R$ +14 +1? +#13900000000000000 +04 +0? +#13950000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100101 ?$ +b10100101 . +b10100101 B$ +b1010010110110101 & +b1010010110110101 -$ +b1010010110110101 7$ +b0 Z$ +0- +b11110101 I$ +b1110010111110101 ) +b1110010111110101 A$ +b1110010111110101 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#14000000000000000 +04 +0? +#14050000000000000 +13$ +1B +1.$ +1$ +1' +b10110101 ?$ +b10110101 . +b10110101 B$ +0G$ +1@$ +b1 M$ +0+ +b10100101 H$ +b1010010111110101 ) +b1010010111110101 A$ +b1010010111110101 N$ +b1 Z$ +b1110010111110101 U$ +b11100101111101011010010010110100 , +b11100101111101011010010010110100 R$ +14 +1? +#14100000000000000 +04 +0? +#14150000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100110 ?$ +b11100110 . +b11100110 B$ +b1110011011110110 & +b1110011011110110 -$ +b1110011011110110 7$ +0K +0P +0R +1W +0Y +0` +0g +0n +0u +0| +0%" +0*" +0," +11" +03" +0:" +0A" +0H" +0O" +0V" +0]" +0b" +0d" +1i" +0k" +0r" +0y" +0"# +0)# +00# +07# +0<# +0># +1C# +b11100110111101101010011010110110 # +b11100110111101101010011010110110 A +b11100110111101101010011010110110 /$ +0E# +0L# +0S# +0Z# +0a# +0h# +0o# +0v# +0}# +0&$ +b10110101 I$ +b1010010110110101 ) +b1010010110110101 A$ +b1010010110110101 N$ +b10 M$ +1+ +0@$ +05$ +b11 I +b1101 J +b10 F +14 +1? +#14200000000000000 +04 +0? +#14250000000000000 +1.$ +1' +b11110110 ?$ +b11110110 . +b11110110 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100110 H$ +b1110011010110101 ) +b1110011010110101 A$ +b1110011010110101 N$ +b10 Z$ +1- +b1010010110110101 V$ +b11100101111101011010010110110101 , +b11100101111101011010010110110101 R$ +14 +1? +#14300000000000000 +04 +0? +#14350000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100110 ?$ +b10100110 . +b10100110 B$ +b1010011010110110 & +b1010011010110110 -$ +b1010011010110110 7$ +b0 Z$ +0- +b11110110 I$ +b1110011011110110 ) +b1110011011110110 A$ +b1110011011110110 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#14400000000000000 +04 +0? +#14450000000000000 +13$ +1B +1.$ +1$ +1' +b10110110 ?$ +b10110110 . +b10110110 B$ +0G$ +1@$ +b1 M$ +0+ +b10100110 H$ +b1010011011110110 ) +b1010011011110110 A$ +b1010011011110110 N$ +b1 Z$ +b1110011011110110 U$ +b11100110111101101010010110110101 , +b11100110111101101010010110110101 R$ +14 +1? +#14500000000000000 +04 +0? +#14550000000000000 +0.$ +03$ +0B +0' +0$ +1G$ +b11100111 ?$ +b11100111 . +b11100111 B$ +b1110011111110111 & +b1110011111110111 -$ +b1110011111110111 7$ +1K +1P +0L +1R +0S +1W +1Y +0Z +1^ +1` +0a +0e +1g +0h +1n +0o +1u +0v +1| +0} +1%" +1*" +0&" +1," +0-" +11" +13" +04" +18" +1:" +0;" +0?" +1A" +0B" +1H" +0I" +1O" +0P" +1V" +0W" +1]" +1b" +0^" +1d" +0e" +1i" +1k" +0l" +1p" +1r" +0s" +0w" +1y" +0z" +1"# +0## +1)# +0*# +10# +01# +17# +1<# +08# +1># +0?# +1C# +1E# +0F# +1J# +1L# +0M# +0Q# +1S# +0T# +1Z# +0[# +1a# +0b# +1h# +0i# +1o# +0p# +1v# +0w# +0{# +b11100111111101111010011110110111 # +b11100111111101111010011110110111 A +b11100111111101111010011110110111 /$ +1}# +0~# +1&$ +0'$ +b10110110 I$ +b1010011010110110 ) +b1010011010110110 A$ +b1010011010110110 N$ +b10 M$ +1+ +0@$ +05$ +b10 I +b1110 J +b1 F +14 +1? +#14600000000000000 +04 +0? +#14650000000000000 +1.$ +1' +b11110111 ?$ +b11110111 . +b11110111 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11100111 H$ +b1110011110110110 ) +b1110011110110110 A$ +b1110011110110110 N$ +b10 Z$ +1- +b1010011010110110 V$ +b11100110111101101010011010110110 , +b11100110111101101010011010110110 R$ +14 +1? +#14700000000000000 +04 +0? +#14750000000000000 +0.$ +03$ +0B +0' +0$ +0T$ +1G$ +b10100111 ?$ +b10100111 . +b10100111 B$ +b1010011110110111 & +b1010011110110111 -$ +b1010011110110111 7$ +b0 Z$ +0- +b11110111 I$ +b1110011111110111 ) +b1110011111110111 A$ +b1110011111110111 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#14800000000000000 +04 +0? +#14850000000000000 +13$ +1B +1.$ +1$ +1' +b10110111 ?$ +b10110111 . +b10110111 B$ +0G$ +1@$ +b1 M$ +0+ +b10100111 H$ +b1010011111110111 ) +b1010011111110111 A$ +b1010011111110111 N$ +b1 Z$ +b1110011111110111 U$ +b11100111111101111010011010110110 , +b11100111111101111010011010110110 R$ +14 +1? +#14900000000000000 +04 +0? +#14950000000000000 +0.$ +03$ +0B +0' +0$ +10$ +1G$ +b11101000 ?$ +b11101000 . +b11101000 B$ +b1110100011111000 & +b1110100011111000 -$ +b1110100011111000 7$ +0K +0P +0R +0W +0Y +0^ +0` +1e +0g +0n +0u +0| +0%" +0*" +0," +01" +03" +08" +0:" +1?" +0A" +0H" +0O" +0V" +0]" +0b" +0d" +0i" +0k" +0p" +0r" +1w" +0y" +0"# +0)# +00# +07# +0<# +0># +0C# +0E# +0J# +0L# +1Q# +0S# +0Z# +0a# +0h# +0o# +0v# +1{# +b1011101000111110001010100010111000 # +b1011101000111110001010100010111000 A +b1011101000111110001010100010111000 /$ +0}# +0&$ +b10110111 I$ +b1010011110110111 ) +b1010011110110111 A$ +b1010011110110111 N$ +b10 M$ +1+ +0@$ +05$ +b1 I +b1111 J +b0 F +14 +1? +#15000000000000000 +04 +0? +#15050000000000000 +1.$ +1' +b11111000 ?$ +b11111000 . +b11111000 B$ +0G$ +1T$ +1@$ +b1 M$ +0+ +b11101000 H$ +b1110100010110111 ) +b1110100010110111 A$ +b1110100010110111 N$ +b10 Z$ +1- +b1010011110110111 V$ +b11100111111101111010011110110111 , +b11100111111101111010011110110111 R$ +14 +1? +#15100000000000000 +04 +0? +#15150000000000000 +0.$ +03$ +0B +0' +18$ +0$ +0T$ +1G$ +b10101000 ?$ +b10101000 . +b10101000 B$ +b101010100010111000 & +b101010100010111000 -$ +b101010100010111000 7$ +b0 Z$ +0- +b11111000 I$ +b1110100011111000 ) +b1110100011111000 A$ +b1110100011111000 N$ +b10 M$ +1+ +0@$ +15$ +14 +1? +#15200000000000000 +04 +0? +#15250000000000000 +1D$ +13$ +1B +00 +1.$ +1$ +1<$ +1' +b10111000 ?$ +b10111000 . +b10111000 B$ +0G$ +1@$ +b1 M$ +0+ +b10101000 H$ +b1010100011111000 ) +b1010100011111000 A$ +b1010100011111000 N$ +b1 Z$ +b1110100011111000 U$ +b11101000111110001010011110110111 , +b11101000111110001010011110110111 R$ +14 +1? +#15300000000000000 +04 +0? +#15350000000000000 +0D$ +10 +0' +0F$ +0<$ +08$ +0$ +0.$ +06$ +12 +03$ +0B +1G$ +1O$ +b11101000 ?$ +b11101000 . +b11101000 B$ +b1110100011111000 & +b1110100011111000 -$ +b1110100011111000 7$ +0>$ +0( +0% +b10111000 I$ +b10 M$ +1+ +1J$ +b101010100010111000 ) +b101010100010111000 A$ +b101010100010111000 N$ +0@$ +05$ +b0 I +b10000 J +1G +14 +1? +#15400000000000000 +04 +0? +#15450000000000000 +0G$ +1T$ +b0 M$ +0+ +1W$ +b10 Z$ +1- +b1010100010111000 V$ +b1011101000111110001010100010111000 , +b1011101000111110001010100010111000 R$ +14 +1? +#15500000000000000 +04 +0? +#15550000000000000 +0T$ +b0 Z$ +0- +14 +1? +#15600000000000000 +04 +0? +#15650000000000000 +14 +1? +#15700000000000000 +04 +0? +#15750000000000000 +14 +1? +#15800000000000000 +04 +0? +#15850000000000000 +14 +1? +#15900000000000000 +04 +0? +#15950000000000000 +14 +1? +#16000000000000000 +04 +0? +#16050000000000000 +14 +1? +#16100000000000000 +04 +0? +#16150000000000000 +14 +1? +#16200000000000000 +04 +0? +#16250000000000000 +14 +1? +#16300000000000000 +04 +0? +#16350000000000000 +14 +1? +#16400000000000000 +04 +0? +#16450000000000000 +14 +1? +#16500000000000000 +04 +0? +#16550000000000000 +14 +1? +#16600000000000000 +04 +0? +#16650000000000000 +14 +1? +#16700000000000000 +04 +0? +#16750000000000000 +14 +1? +#16800000000000000 +04 +0? +#16850000000000000 +14 +1? +#16900000000000000 +04 +0? +#16950000000000000 +14 +1? +#17000000000000000 +04 +0? +#17050000000000000 +14 +1? +#17100000000000000 +04 +0? +#17150000000000000 +14 +1? +#17200000000000000 +04 +0? +#17250000000000000 +14 +1? +#17300000000000000 +04 +0? +#17350000000000000 +14 +1? +#17400000000000000 +04 +0? +#17450000000000000 +14 +1? +#17500000000000000 +04 +0? +#17550000000000000 +14 +1? +#17600000000000000 +04 +0? +#17650000000000000 +14 +1? +#17700000000000000 +04 +0? +#17750000000000000 +14 +1? +#17800000000000000 +04 +0? +#17850000000000000 +14 +1? +#17900000000000000 +04 +0? +#17950000000000000 +14 +1? +#18000000000000000 +04 +0? +#18050000000000000 +14 +1? +#18100000000000000 +04 +0? +#18150000000000000 +14 +1? +#18200000000000000 +04 +0? +#18250000000000000 +14 +1? +#18300000000000000 +04 +0? +#18350000000000000 +14 +1? +#18400000000000000 +04 +0? +#18450000000000000 +14 +1? +#18500000000000000 +04 +0? +#18550000000000000 +14 +1? +#18600000000000000 +04 +0? +#18650000000000000 +14 +1? +#18700000000000000 +04 +0? +#18750000000000000 +14 +1? +#18800000000000000 +04 +0? +#18850000000000000 +14 +1? +#18900000000000000 +04 +0? +#18950000000000000 +14 +1? +#19000000000000000 +04 +0? +#19050000000000000 +14 +1? +#19100000000000000 +04 +0? +#19150000000000000 +14 +1? +#19200000000000000 +04 +0? +#19250000000000000 +14 +1? +#19300000000000000 +04 +0? +#19350000000000000 +14 +1? +#19400000000000000 +04 +0? +#19450000000000000 +14 +1? +#19500000000000000 +04 +0? +#19550000000000000 +14 +1? +#19600000000000000 +04 +0? +#19650000000000000 +14 +1? +#19700000000000000 +04 +0? +#19750000000000000 +14 +1? +#19800000000000000 +04 +0? +#19850000000000000 +14 +1? +#19900000000000000 +04 +0? +#19950000000000000 +14 +1? +#20000000000000000 +04 +0? diff --git a/usrp2/fifo/fifo_short.v b/usrp2/fifo/fifo_short.v new file mode 100644 index 000000000..53a7603c7 --- /dev/null +++ b/usrp2/fifo/fifo_short.v @@ -0,0 +1,95 @@ + +module fifo_short + #(parameter WIDTH=32) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + + output reg [4:0] space, + output reg [4:0] occupied); + + reg full, empty; + wire write = src_rdy_i & dst_rdy_o; + wire read = dst_rdy_i & src_rdy_o; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + + reg [3:0] a; + genvar i; + + generate + for (i=0;i<WIDTH;i=i+1) + begin : gen_srl16 + SRL16E + srl16e(.Q(dataout[i]), + .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]), + .CE(write),.CLK(clk),.D(datain[i])); + end + endgenerate + + always @(posedge clk) + if(reset) + begin + a <= 0; + empty <= 1; + full <= 0; + end + else if(clear) + begin + a <= 0; + empty <= 1; + full<= 0; + end + else if(read & ~write) + begin + full <= 0; + if(a==0) + empty <= 1; + else + a <= a - 1; + end + else if(write & ~read) + begin + empty <= 0; + if(~empty) + a <= a + 1; + if(a == 14) + full <= 1; + end + + // NOTE will fail if you write into a full fifo or read from an empty one + + ////////////////////////////////////////////////////////////// + // space and occupied are used for diagnostics, not + // guaranteed correct + + //assign space = full ? 0 : empty ? 16 : 15-a; + //assign occupied = empty ? 0 : full ? 16 : a+1; + + always @(posedge clk) + if(reset) + space <= 16; + else if(clear) + space <= 16; + else if(read & ~write) + space <= space + 1; + else if(write & ~read) + space <= space - 1; + + always @(posedge clk) + if(reset) + occupied <= 0; + else if(clear) + occupied <= 0; + else if(read & ~write) + occupied <= occupied - 1; + else if(write & ~read) + occupied <= occupied + 1; + +endmodule // fifo_short + diff --git a/usrp2/fifo/fifo_spec.txt b/usrp2/fifo/fifo_spec.txt new file mode 100644 index 000000000..133b9fa8e --- /dev/null +++ b/usrp2/fifo/fifo_spec.txt @@ -0,0 +1,36 @@ + + +FIFO and Buffer Interface Spec + +Buffer Interface Data Wires -- matches fifo36 + DATA[31:0] + FLAGS[3:0] + Bit 0 SOP + Bit 1 EOP + If SOP=1 && EOP=1, OCC contains error flags + Bits 3:2 OCC[1:0] --> 00 = all 4 bytes + 01 = 1 byte + 10 = 2 bytes + 11 = 3 bytes + +fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} + OCC same as buffer interface + +fifo19 --> {OCC,EOP,SOP,DATA[15:0]} + Doesn't fit well into BRAM, dist RAM ok + OCC = 1 means last word is half full + = 0 means last word is full + +fifo18 --> {EOP,SOP,DATA[15:0]} + No half-word capability? Should we drop sop instead? + +Control Wires - Data into FIFO + SRC_RDY_i Upstream has data for me + DST_RDY_o I have space + Transfer occurs if SRC_RDI_i && DST_RDY_o + +Control Wires - Data out of FIFO + SRC_RDY_o I have data for downstream + DST_RDY_i Downstream has space + Transfer occurs if SRC_RDI_o && DST_RDY_i + diff --git a/usrp2/fifo/fifo_tb.v b/usrp2/fifo/fifo_tb.v new file mode 100644 index 000000000..f561df7fa --- /dev/null +++ b/usrp2/fifo/fifo_tb.v @@ -0,0 +1,158 @@ +module fifo_new_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [31:0] f36_data = 0; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out, f36_out2; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + + wire i1_sr, i1_dr; + wire i2_sr, i2_dr; + wire i3_sr, i3_dr; + reg i4_dr = 0; + wire i4_sr; + + wire [35:0] i1, i4; + wire [18:0] i2, i3; + + wire [7:0] ll_data; + wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; + + fifo_short #(.WIDTH(36)) fifo_short1 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); + + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), + .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); + + fifo19_to_ll8 fifo19_to_ll8 + (.clk(clk),.reset(rst),.clear(clear), + .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); + + ll8_to_fifo19 ll8_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), + .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk),.reset(rst),.clear(clear), + .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), + .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); + + task ReadFromFIFO36; + begin + $display("Read from FIFO36"); + #1 i4_dr <= 1; + while(1) + begin + while(~i4_sr) + @(posedge clk); + $display("Read: %h",i4); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + reg [15:0] count; + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + begin + count <= 4; + src_rdy_f36i <= 1; + f36_data <= data_start; + f36_sof <= 1; + f36_eof <= 0; + f36_occ <= 0; + + $display("Put Packet in FIFO36"); + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered First Line"); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data <= f36_data + 32'h01010101; + count <= count + 4; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered New Line"); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("PPI_FIFO36: Entered Last Line"); + end + endtask // PutPacketInFIFO36 + + initial $dumpfile("fifo_new_tb.vcd"); + initial $dumpvars(0,fifo_new_tb); + + initial + begin + @(negedge rst); + //#10000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + ReadFromFIFO36; + end + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + + initial #20000 $finish; +endmodule // longfifo_tb diff --git a/usrp2/fifo/ll8_shortfifo.v b/usrp2/fifo/ll8_shortfifo.v new file mode 100644 index 000000000..39ada9a4f --- /dev/null +++ b/usrp2/fifo/ll8_shortfifo.v @@ -0,0 +1,13 @@ + + +module ll8_shortfifo + (input clk, input reset, input clear, + input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, + output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); + + fifo_short #(.WIDTH(11)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + +endmodule // ll8_shortfifo diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v new file mode 100644 index 000000000..af3b91afb --- /dev/null +++ b/usrp2/fifo/ll8_to_fifo19.v @@ -0,0 +1,73 @@ + +module ll8_to_fifo19 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [18:0] f19_data, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + localparam XFER_EMPTY = 0; + localparam XFER_HALF = 1; + localparam XFER_HALF_WRITE = 3; + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; + wire xfer_in = ll_src_rdy & ll_dst_rdy; + + reg hold_sof; + wire f19_sof, f19_eof, f19_occ; + + reg [1:0] state; + reg [7:0] hold_reg; + + always @(posedge clk) + if(ll_src_rdy & (state==XFER_EMPTY)) + hold_reg <= ll_data; + + always @(posedge clk) + if(ll_sof & (state==XFER_EMPTY)) + hold_sof <= 1; + else if(xfer_out) + hold_sof <= 0; + + always @(posedge clk) + if(reset | clear) + state <= XFER_EMPTY; + else + case(state) + XFER_EMPTY : + if(ll_src_rdy) + if(ll_eof) + state <= XFER_HALF_WRITE; + else + state <= XFER_HALF; + XFER_HALF : + if(ll_src_rdy & f19_dst_rdy_i) + state <= XFER_EMPTY; + XFER_HALF_WRITE : + if(f19_dst_rdy_i) + state <= XFER_EMPTY; + endcase // case (state) + + assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i); + assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy); + + assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF)); + assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof; + assign f19_occ = (state == XFER_HALF_WRITE); + + assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data}; + +endmodule // ll8_to_fifo19 + diff --git a/usrp2/fifo/ll8_to_fifo36.v b/usrp2/fifo/ll8_to_fifo36.v new file mode 100644 index 000000000..108daa903 --- /dev/null +++ b/usrp2/fifo/ll8_to_fifo36.v @@ -0,0 +1,97 @@ + +module ll8_to_fifo36 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [35:0] f36_data, + output f36_src_rdy_o, + input f36_dst_rdy_i ); + + wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + reg f36_sof, f36_eof; + reg [1:0] f36_occ; + + + reg [2:0] state; + reg [7:0] dat0, dat1, dat2, dat3; + + always @(posedge clk) + if(ll_src_rdy & ((state==0)|f36_write)) + f36_sof <= ll_sof; + + always @(posedge clk) + if(ll_src_rdy & ((state !=4)|f36_write)) + f36_eof <= ll_eof; + + always @(posedge clk) + if(ll_eof) + f36_occ <= state[1:0] + 1; + else + f36_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(ll_src_rdy) + case(state) + 0 : + if(ll_eof) + state <= 4; + else + state <= 1; + 1 : + if(ll_eof) + state <= 4; + else + state <= 2; + 2 : + if(ll_eof) + state <= 4; + else + state <= 3; + 3 : state <= 4; + 4 : + if(f36_dst_rdy_i) + if(ll_eof) + state <= 4; + else + state <= 1; + endcase // case(state) + else + if(f36_write) + state <= 0; + + always @(posedge clk) + if(ll_src_rdy & (state==3)) + dat3 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==2)) + dat2 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==1)) + dat1 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & ((state==0) | f36_write)) + dat0 <= ll_data; + + assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); + assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess + assign f36_src_rdy_o = (state == 4); + +endmodule // ll8_to_fifo36 |