summaryrefslogtreecommitdiffstats
path: root/usrp2/fifo
diff options
context:
space:
mode:
Diffstat (limited to 'usrp2/fifo')
-rw-r--r--usrp2/fifo/buffer_int2.v11
-rw-r--r--usrp2/fifo/dsp_framer36.v5
-rw-r--r--usrp2/fifo/fifo18_to_fifo36.v20
-rw-r--r--usrp2/fifo/fifo19_to_fifo36.v74
-rw-r--r--usrp2/fifo/fifo36_to_fifo19.v48
-rw-r--r--usrp2/fifo/fifo36_to_ll8.v73
-rw-r--r--usrp2/fifo/ll8_to_fifo19.v76
-rw-r--r--usrp2/fifo/packet_router.v61
8 files changed, 219 insertions, 149 deletions
diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v
index 765b125fb..c73456b74 100644
--- a/usrp2/fifo/buffer_int2.v
+++ b/usrp2/fifo/buffer_int2.v
@@ -32,12 +32,13 @@ module buffer_int2
);
reg [BUF_SIZE-1:0] rd_addr, wr_addr;
+ wire [BUF_SIZE-1:0] rd_addr_next = rd_addr + 1;
wire [31:0] ctrl;
wire wr_done, wr_error, wr_idle;
wire rd_done, rd_error, rd_idle;
wire we, en, go;
- reg [BUF_SIZE-1:0] lastline;
+ reg [BUF_SIZE-1:0] rd_length;
wire read = ctrl[3];
wire rd_clear = ctrl[2];
wire write = ctrl[1];
@@ -72,13 +73,13 @@ module buffer_int2
begin
rd_addr <= 0;
rd_state <= PRE_READ;
- lastline <= ctrl[15+BUF_SIZE:16];
+ rd_length <= ctrl[15+BUF_SIZE:16];
end
PRE_READ :
begin
rd_state <= READING;
- rd_addr <= rd_addr + 1;
+ rd_addr <= rd_addr_next;
rd_occ <= 2'b00;
rd_sop <= 1;
rd_eop <= 0;
@@ -88,8 +89,8 @@ module buffer_int2
if(rd_ready_i)
begin
rd_sop <= 0;
- rd_addr <= rd_addr + 1;
- if(rd_addr == lastline)
+ rd_addr <= rd_addr_next;
+ if(rd_addr_next == rd_length)
begin
rd_eop <= 1;
// FIXME assign occ here
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v
index 34a05d91e..f7d7fb68e 100644
--- a/usrp2/fifo/dsp_framer36.v
+++ b/usrp2/fifo/dsp_framer36.v
@@ -2,7 +2,7 @@
// Frame DSP packets with a header line to be handled by the protocol machine
module dsp_framer36
- #(parameter BUF_SIZE = 9)
+ #(parameter BUF_SIZE = 9, parameter PORT_SEL = 0)
(
input clk, input rst, input clr,
input [35:0] inp_data, input inp_valid, output inp_ready,
@@ -29,8 +29,9 @@ module dsp_framer36
//The header is generated here from the count.
wire [31:0] dsp_frm_data_bram;
wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
+ wire [1:0] port_sel_bits = PORT_SEL;
assign out_data =
- (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
+ (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 13'b0, port_sel_bits, 1'b1, dsp_frm_bytes} : (
(dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : (
{4'b0000, dsp_frm_data_bram}));
assign out_valid = (
diff --git a/usrp2/fifo/fifo18_to_fifo36.v b/usrp2/fifo/fifo18_to_fifo36.v
deleted file mode 100644
index 25bb215a1..000000000
--- a/usrp2/fifo/fifo18_to_fifo36.v
+++ /dev/null
@@ -1,20 +0,0 @@
-
-// For now just assume FIFO18 is same as FIFO19 without occupancy bit
-
-module fifo18_to_fifo36
- (input clk, input reset, input clear,
- input [17:0] f18_datain,
- input f18_src_rdy_i,
- output f18_dst_rdy_o,
-
- output [35:0] f36_dataout,
- output f36_src_rdy_o,
- input f36_dst_rdy_i
- );
-
- fifo19_to_fifo36 fifo19_to_fifo36
- (.clk(clk), .reset(reset), .clear(clear),
- .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o),
- .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) );
-
-endmodule // fifo18_to_fifo36
diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v
index ae2edddc7..502821435 100644
--- a/usrp2/fifo/fifo19_to_fifo36.v
+++ b/usrp2/fifo/fifo19_to_fifo36.v
@@ -15,60 +15,73 @@ module fifo19_to_fifo36
input f36_dst_rdy_i,
output [31:0] debug
);
-
- reg f36_sof, f36_eof;
- reg [1:0] f36_occ;
+ // Shortfifo on input to guarantee no deadlock
+ wire [18:0] f19_data_int;
+ wire f19_src_rdy_int, f19_dst_rdy_int;
+
+ fifo_short #(.WIDTH(19)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o),
+ .dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int),
+ .space(),.occupied() );
+
+ // Actual f19 to f36 which could deadlock if not connected to shortfifos
+ reg f36_sof_int, f36_eof_int;
+ reg [1:0] f36_occ_int;
+ wire [35:0] f36_data_int;
+ wire f36_src_rdy_int, f36_dst_rdy_int;
+
reg [1:0] state;
reg [15:0] dat0, dat1;
- wire f19_sof = f19_datain[16];
- wire f19_eof = f19_datain[17];
- wire f19_occ = f19_datain[18];
+ wire f19_sof_int = f19_data_int[16];
+ wire f19_eof_int = f19_data_int[17];
+ wire f19_occ_int = f19_data_int[18];
- wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+ wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int;
always @(posedge clk)
- if(f19_src_rdy_i & ((state==0)|xfer_out))
- f36_sof <= f19_sof;
+ if(f19_src_rdy_int & ((state==0)|xfer_out))
+ f36_sof_int <= f19_sof_int;
always @(posedge clk)
- if(f19_src_rdy_i & ((state != 2)|xfer_out))
- f36_eof <= f19_eof;
+ if(f19_src_rdy_int & ((state != 2)|xfer_out))
+ f36_eof_int <= f19_eof_int;
always @(posedge clk)
if(reset)
begin
state <= 0;
- f36_occ <= 0;
+ f36_occ_int <= 0;
end
else
- if(f19_src_rdy_i)
+ if(f19_src_rdy_int)
case(state)
0 :
begin
- dat0 <= f19_datain;
- if(f19_eof)
+ dat0 <= f19_data_int;
+ if(f19_eof_int)
begin
state <= 2;
- f36_occ <= f19_occ ? 2'b01 : 2'b10;
+ f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
end
else
state <= 1;
end
1 :
begin
- dat1 <= f19_datain;
+ dat1 <= f19_data_int;
state <= 2;
- if(f19_eof)
- f36_occ <= f19_occ ? 2'b11 : 2'b00;
+ if(f19_eof_int)
+ f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00;
end
2 :
if(xfer_out)
begin
- dat0 <= f19_datain;
- if(f19_eof) // remain in state 2 if we are at eof
- f36_occ <= f19_occ ? 2'b01 : 2'b10;
+ dat0 <= f19_data_int;
+ if(f19_eof_int) // remain in state 2 if we are at eof
+ f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
else
state <= 1;
end
@@ -77,14 +90,21 @@ module fifo19_to_fifo36
if(xfer_out)
begin
state <= 0;
- f36_occ <= 0;
+ f36_occ_int <= 0;
end
- assign f19_dst_rdy_o = xfer_out | (state != 2);
- assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
- {f36_occ,f36_eof,f36_sof,dat0,dat1};
- assign f36_src_rdy_o = (state == 2);
+ assign f19_dst_rdy_int = xfer_out | (state != 2);
+ assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} :
+ {f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1};
+ assign f36_src_rdy_int = (state == 2);
assign debug = state;
+
+ // Shortfifo on output to guarantee no deadlock
+ fifo_short #(.WIDTH(36)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
+ .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
+ .space(),.occupied() );
endmodule // fifo19_to_fifo36
diff --git a/usrp2/fifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v
index e016fe2c6..0e9b2d442 100644
--- a/usrp2/fifo/fifo36_to_fifo19.v
+++ b/usrp2/fifo/fifo36_to_fifo19.v
@@ -13,25 +13,37 @@ module fifo36_to_fifo19
output [18:0] f19_dataout,
output f19_src_rdy_o,
input f19_dst_rdy_i );
-
- wire f36_sof = f36_datain[32];
- wire f36_eof = f36_datain[33];
- wire [1:0] f36_occ = f36_datain[35:34];
+
+ wire [18:0] f19_data_int;
+ wire f19_src_rdy_int, f19_dst_rdy_int;
+ wire [35:0] f36_data_int;
+ wire f36_src_rdy_int, f36_dst_rdy_int;
+
+ // Shortfifo on input to guarantee no deadlock
+ fifo_short #(.WIDTH(36)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+ .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+ .space(),.occupied() );
+
+ // Main fifo36_to_fifo19, needs shortfifos to guarantee no deadlock
+ wire [1:0] f36_occ_int = f36_data_int[35:34];
+ wire f36_sof_int = f36_data_int[32];
+ wire f36_eof_int = f36_data_int[33];
reg phase;
+ wire half_line = f36_eof_int & ((f36_occ_int==1)|(f36_occ_int==2));
- wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
-
- assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
- assign f19_dataout[16] = phase ? 0 : f36_sof;
- assign f19_dataout[17] = phase ? f36_eof : half_line;
- assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+ assign f19_data_int[15:0] = (LE ^ phase) ? f36_data_int[15:0] : f36_data_int[31:16];
+ assign f19_data_int[16] = phase ? 0 : f36_sof_int;
+ assign f19_data_int[17] = phase ? f36_eof_int : half_line;
+ assign f19_data_int[18] = f19_data_int[17] & ((f36_occ_int==1)|(f36_occ_int==3));
- assign f19_src_rdy_o = f36_src_rdy_i;
- assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i;
+ assign f19_src_rdy_int = f36_src_rdy_int;
+ assign f36_dst_rdy_int = (phase | half_line) & f19_dst_rdy_int;
- wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i;
- wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+ wire f19_xfer = f19_src_rdy_int & f19_dst_rdy_int;
+ wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int;
always @(posedge clk)
if(reset)
@@ -41,5 +53,11 @@ module fifo36_to_fifo19
else if(f19_xfer)
phase <= 1;
-
+ // Shortfifo on output to guarantee no deadlock
+ fifo_short #(.WIDTH(19)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
+ .dataout(f19_dataout), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
+ .space(),.occupied() );
+
endmodule // fifo36_to_fifo19
diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v
index 9604d0e38..f1f0032e4 100644
--- a/usrp2/fifo/fifo36_to_ll8.v
+++ b/usrp2/fifo/fifo36_to_ll8.v
@@ -5,24 +5,31 @@ module fifo36_to_ll8
input f36_src_rdy_i,
output f36_dst_rdy_o,
- output reg [7:0] ll_data,
- output ll_sof_n,
- output ll_eof_n,
- output ll_src_rdy_n,
- input ll_dst_rdy_n,
+ output [7:0] ll_data,
+ output ll_sof,
+ output ll_eof,
+ output ll_src_rdy,
+ input ll_dst_rdy,
output [31:0] debug);
- wire ll_sof, ll_eof, ll_src_rdy;
- assign ll_sof_n = ~ll_sof;
- assign ll_eof_n = ~ll_eof;
- assign ll_src_rdy_n = ~ll_src_rdy;
- wire ll_dst_rdy = ~ll_dst_rdy_n;
+ // Shortfifo on input to guarantee no deadlock
+ wire [35:0] f36_data_int;
+ wire f36_src_rdy_int, f36_dst_rdy_int;
+ reg [7:0] ll_data_int;
+ wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
+
+ fifo_short #(.WIDTH(36)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+ .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+ .space(),.occupied() );
- wire f36_sof = f36_data[32];
- wire f36_eof = f36_data[33];
- wire f36_occ = f36_data[35:34];
- wire advance, end_early;
+ // Actual fifo36 to ll8, can deadlock if not connected to shortfifo
+ wire f36_sof_int = f36_data_int[32];
+ wire f36_eof_int = f36_data_int[33];
+ wire f36_occ_int = f36_data_int[35:34];
+ wire advance, end_early;
reg [1:0] state;
assign debug = {29'b0,state};
@@ -31,29 +38,37 @@ module fifo36_to_ll8
state <= 0;
else
if(advance)
- if(ll_eof)
+ if(ll_eof_int)
state <= 0;
else
state <= state + 1;
always @*
case(state)
- 0 : ll_data = f36_data[31:24];
- 1 : ll_data = f36_data[23:16];
- 2 : ll_data = f36_data[15:8];
- 3 : ll_data = f36_data[7:0];
- default : ll_data = f36_data[31:24];
+ 0 : ll_data_int = f36_data_int[31:24];
+ 1 : ll_data_int = f36_data_int[23:16];
+ 2 : ll_data_int = f36_data_int[15:8];
+ 3 : ll_data_int = f36_data_int[7:0];
+ default : ll_data_int = f36_data_int[31:24];
endcase // case (state)
- assign ll_sof = (state==0) & f36_sof;
- assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) |
- ((state==1)&(f36_occ==2)) |
- ((state==2)&(f36_occ==3)) |
+ assign ll_sof_int = (state==0) & f36_sof_int;
+ assign ll_eof_int = f36_eof_int & (((state==0)&(f36_occ_int==1)) |
+ ((state==1)&(f36_occ_int==2)) |
+ ((state==2)&(f36_occ_int==3)) |
(state==3));
- assign ll_src_rdy = f36_src_rdy_i;
-
- assign advance = ll_src_rdy & ll_dst_rdy;
- assign f36_dst_rdy_o = advance & ((state==3)|ll_eof);
+ assign ll_src_rdy_int = f36_src_rdy_int;
-endmodule // ll8_to_fifo36
+ assign advance = ll_src_rdy_int & ll_dst_rdy_int;
+ assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int);
+
+ // Short FIFO on output to guarantee no deadlock
+ ll8_shortfifo tail_fifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int),
+ .error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int),
+ .dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+ .error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy));
+
+endmodule // fifo36_to_ll8
diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v
index af3b91afb..ac8ac19a6 100644
--- a/usrp2/fifo/ll8_to_fifo19.v
+++ b/usrp2/fifo/ll8_to_fifo19.v
@@ -2,41 +2,47 @@
module ll8_to_fifo19
(input clk, input reset, input clear,
input [7:0] ll_data,
- input ll_sof_n,
- input ll_eof_n,
- input ll_src_rdy_n,
- output ll_dst_rdy_n,
+ input ll_sof,
+ input ll_eof,
+ input ll_src_rdy,
+ output ll_dst_rdy,
output [18:0] f19_data,
output f19_src_rdy_o,
input f19_dst_rdy_i );
+
+ // Short FIFO on input to guarantee no deadlock
+ wire [7:0] ll_data_int;
+ wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
+ ll8_shortfifo head_fifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof),
+ .error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy),
+ .dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int),
+ .error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int));
+
+ // Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo
localparam XFER_EMPTY = 0;
localparam XFER_HALF = 1;
localparam XFER_HALF_WRITE = 3;
- // Why anybody would use active low in an FPGA is beyond me...
- wire ll_sof = ~ll_sof_n;
- wire ll_eof = ~ll_eof_n;
- wire ll_src_rdy = ~ll_src_rdy_n;
- wire ll_dst_rdy;
- assign ll_dst_rdy_n = ~ll_dst_rdy;
-
- wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i;
- wire xfer_in = ll_src_rdy & ll_dst_rdy;
-
- reg hold_sof;
- wire f19_sof, f19_eof, f19_occ;
+ wire [18:0] f19_data_int;
+ wire f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int;
+
+ wire xfer_out = f19_src_rdy_int & f19_dst_rdy_int;
+ wire xfer_in = ll_src_rdy_int & ll_dst_rdy_int;
+ reg hold_sof;
- reg [1:0] state;
- reg [7:0] hold_reg;
+ reg [1:0] state;
+ reg [7:0] hold_reg;
always @(posedge clk)
- if(ll_src_rdy & (state==XFER_EMPTY))
- hold_reg <= ll_data;
+ if(ll_src_rdy_int & (state==XFER_EMPTY))
+ hold_reg <= ll_data_int;
always @(posedge clk)
- if(ll_sof & (state==XFER_EMPTY))
+ if(ll_sof_int & (state==XFER_EMPTY))
hold_sof <= 1;
else if(xfer_out)
hold_sof <= 0;
@@ -47,27 +53,35 @@ module ll8_to_fifo19
else
case(state)
XFER_EMPTY :
- if(ll_src_rdy)
- if(ll_eof)
+ if(ll_src_rdy_int)
+ if(ll_eof_int)
state <= XFER_HALF_WRITE;
else
state <= XFER_HALF;
XFER_HALF :
- if(ll_src_rdy & f19_dst_rdy_i)
+ if(ll_src_rdy_int & f19_dst_rdy_int)
state <= XFER_EMPTY;
XFER_HALF_WRITE :
- if(f19_dst_rdy_i)
+ if(f19_dst_rdy_int)
state <= XFER_EMPTY;
endcase // case (state)
- assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
- assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+ assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int);
+ assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int);
- assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF));
- assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof;
- assign f19_occ = (state == XFER_HALF_WRITE);
+ assign f19_sof_int = hold_sof | (ll_sof_int & (state==XFER_HALF));
+ assign f19_eof_int = (state == XFER_HALF_WRITE) | ll_eof_int;
+ assign f19_occ_int = (state == XFER_HALF_WRITE);
- assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
+ assign f19_data_int = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int};
+
+ // Shortfifo on output to guarantee no deadlock
+ fifo_short #(.WIDTH(19)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
+ .dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
+ .space(),.occupied() );
+
endmodule // ll8_to_fifo19
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index 161b59016..61f90d3cf 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -33,7 +33,8 @@ module packet_router
// Input Interfaces (in to router)
input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready,
- input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready,
+ input [35:0] dsp0_inp_data, input dsp0_inp_valid, output dsp0_inp_ready,
+ input [35:0] dsp1_inp_data, input dsp1_inp_valid, output dsp1_inp_ready,
input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready,
@@ -83,11 +84,11 @@ module packet_router
);
//setting register to program the UDP data ports
- wire [15:0] dsp0_udp_port, dsp1_udp_port;
- setting_reg #(.my_addr(CTRL_BASE+2)) sreg_data_ports(
+ wire [15:0] dsp_udp_port;
+ setting_reg #(.my_addr(CTRL_BASE+2), .width(16)) sreg_data_ports(
.clk(stream_clk),.rst(stream_rst),
.strobe(set_stb),.addr(set_addr),.in(set_data),
- .out({dsp1_udp_port, dsp0_udp_port}),.changed()
+ .out(dsp_udp_port),.changed()
);
//assign status output signals
@@ -116,6 +117,11 @@ module packet_router
wire _eth_inp_valid;
wire _eth_inp_ready;
+ // dummy signals to connect fifo_short
+ wire [35:0] _com_inp_data;
+ wire _com_inp_valid;
+ wire _com_inp_ready;
+
valve36 eth_inp_valve (
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag),
.data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready),
@@ -126,10 +132,17 @@ module packet_router
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
.data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready),
.data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready),
- .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready),
+ .data0_o(_com_inp_data), .src0_rdy_o(_com_inp_valid), .dst0_rdy_i(_com_inp_ready),
.data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready)
);
+ // short fifo in the packet inspection path to help timing
+ fifo_short #(.WIDTH(36)) com_inp_fifo
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .datain(_com_inp_data), .src_rdy_i(_com_inp_valid), .dst_rdy_o(_com_inp_ready),
+ .dataout(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready),
+ .space(), .occupied() );
+
////////////////////////////////////////////////////////////////////
// Communication output sink crossbar
// When in master mode:
@@ -172,30 +185,33 @@ module packet_router
////////////////////////////////////////////////////////////////////
//streaming signals from the dsp framer to the combiner
- wire [35:0] dsp_frm_data;
- wire dsp_frm_valid;
- wire dsp_frm_ready;
+ wire [35:0] dsp0_frm_data, dsp1_frm_data;
+ wire dsp0_frm_valid, dsp1_frm_valid;
+ wire dsp0_frm_ready, dsp1_frm_ready;
//dummy signals to join the the muxes below
wire [35:0] _combiner0_data, _combiner1_data;
wire _combiner0_valid, _combiner1_valid;
wire _combiner0_ready, _combiner1_ready;
- fifo36_mux _com_output_combiner0(
+ fifo36_mux #(.prio(0)) // No priority, fair sharing
+ _com_output_combiner0(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready),
- .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready),
+ .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready),
+ .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
.data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
);
- fifo36_mux _com_output_combiner1(
+ fifo36_mux #(.prio(0)) // No priority, fair sharing
+ _com_output_combiner1(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here
- .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
+ .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready),
+ .data1_i(dsp1_frm_data), .src1_rdy_i(dsp1_frm_valid), .dst1_rdy_o(dsp1_frm_ready),
.data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
);
- fifo36_mux com_output_source(
+ fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp
+ com_output_source(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
.data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
.data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
@@ -364,7 +380,7 @@ module packet_router
end
//UDP data port and VRT:
- else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
+ else if ((com_insp_dregs_udp_dst_port == dsp_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
com_insp_dest <= COM_INSP_DEST_DSP;
com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
end
@@ -448,11 +464,16 @@ module packet_router
////////////////////////////////////////////////////////////////////
// DSP input framer
////////////////////////////////////////////////////////////////////
+ dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(0)) dsp0_framer36(
+ .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+ .inp_data(dsp0_inp_data), .inp_valid(dsp0_inp_valid), .inp_ready(dsp0_inp_ready),
+ .out_data(dsp0_frm_data), .out_valid(dsp0_frm_valid), .out_ready(dsp0_frm_ready)
+ );
- dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36(
+ dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(2)) dsp1_framer36(
.clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
- .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready),
- .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready)
+ .inp_data(dsp1_inp_data), .inp_valid(dsp1_inp_valid), .inp_ready(dsp1_inp_ready),
+ .out_data(dsp1_frm_data), .out_valid(dsp1_frm_valid), .out_ready(dsp1_frm_ready)
);
////////////////////////////////////////////////////////////////////
@@ -508,7 +529,7 @@ module packet_router
assign debug = {
//inputs to the router (8)
- dsp_inp_ready, dsp_inp_valid,
+ dsp0_inp_ready, dsp0_inp_valid,
ser_inp_ready, ser_inp_valid,
eth_inp_ready, eth_inp_valid,
cpu_inp_ready, cpu_inp_valid,
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-08 10:21:49 +0000