diff options
Diffstat (limited to 'usrp2/extramfifo')
| -rw-r--r-- | usrp2/extramfifo/.gitignore | 3 | ||||
| -rwxr-xr-x[-rw-r--r--] | usrp2/extramfifo/fifo_extram36_tb.build | 2 | ||||
| -rw-r--r-- | usrp2/extramfifo/fifo_extram36_tb.v | 6 | ||||
| -rwxr-xr-x[-rw-r--r--] | usrp2/extramfifo/fifo_extram_tb.build | 2 |
4 files changed, 8 insertions, 5 deletions
diff --git a/usrp2/extramfifo/.gitignore b/usrp2/extramfifo/.gitignore new file mode 100644 index 000000000..94bbf6dcc --- /dev/null +++ b/usrp2/extramfifo/.gitignore @@ -0,0 +1,3 @@ +fifo_extram36_tb +fifo_extram_tb +*.vcd diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build index 699591889..ac9369758 100644..100755 --- a/usrp2/extramfifo/fifo_extram36_tb.build +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v index f28c35e4f..e5f8cef4c 100644 --- a/usrp2/extramfifo/fifo_extram36_tb.v +++ b/usrp2/extramfifo/fifo_extram36_tb.v @@ -296,8 +296,8 @@ module fifo_extram36_tb(); end src_rdy_f36i = 0; f36_data = 32'bX; -//* if (put_index > 19'h3ff00) -//* Verbose = 1'b1; +// if (put_index > 19'h3ff00) +// Verbose = 1'b1; end endtask // task_WriteFIFO36 @@ -385,7 +385,7 @@ module fifo_extram36_tb(); $finish; end - */ + initial begin diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build index e87217e5c..5607c8691 100644..100755 --- a/usrp2/extramfifo/fifo_extram_tb.build +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |