3 files changed, 17 insertions, 9 deletions

diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index b17fde10b..2af59a75d 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -38,7 +38,8 @@ module ext_fifo
      output [INT_WIDTH-1:0] dataout,
      output src_rdy_o,               // not EMPTY
      input dst_rdy_i,                 // READ
-     output reg [31:0] debug
+     output reg [31:0] debug,
+     output reg [31:0] debug2
      );
 
    wire [EXT_WIDTH-1:0] write_data;
@@ -111,9 +112,12 @@ module ext_fifo
    assign  src_rdy_o = ~empty2;
 
    always @ (posedge int_clk)
-     debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i };
+     debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
    
    always @ (posedge ext_clk)
-     debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] };
+     debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
 
+   always@ (posedge ext_clk)
+//     debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+       debug2[31:0] <= 0;
 endmodule // ext_fifo
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v
index 62229e6c2..4c009d980 100644
--- a/usrp2/extramfifo/nobl_fifo.v
+++ b/usrp2/extramfifo/nobl_fifo.v
@@ -47,7 +47,7 @@ module nobl_fifo
 	  capacity <= (1 << FIFO_DEPTH) - 1;
 	  wr_pointer <= 0;
 	  rd_pointer <= 0;
-	  space_avail <= 0;
+	  space_avail <= 1;
 	  data_avail_int <= 0;
        end
      else	  
@@ -56,7 +56,7 @@ module nobl_fifo
 	  // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision)
 	  space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );
 	  // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO.
-	  data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1))  || ((capacity == ((1 << FIFO_DEPTH)-2)) && read)  );
+	  data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1))  || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read))  );
 	  wr_pointer <= wr_pointer + write;
 	  rd_pointer <= rd_pointer + (~write && read); 
 	  capacity <= capacity - write + (~write && read) ;
diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 24d463b1e..391a841e8 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -9,11 +9,11 @@ module nobl_if
      output [WIDTH-1:0] RAM_D_po,
      output reg RAM_D_poe,
      output [DEPTH-1:0] RAM_A,
-     output RAM_WEn,
+     output reg RAM_WEn,
      output RAM_CENn,
      output RAM_LDn,
      output RAM_OEn,
-     output RAM_CE1n,
+     output reg RAM_CE1n,
      input [DEPTH-1:0] address,
      input [WIDTH-1:0] data_out,
      output reg [WIDTH-1:0] data_in,
@@ -54,11 +54,15 @@ module nobl_if
      else
        begin
 	  enable_pipe1 <= enable;
+	  RAM_CE1n <= ~enable;  // Creates IOB flob
+	  
 	  
 	  if (enable)
 	    begin
 	       address_pipe1 <= address;
 	       write_pipe1 <= write;
+	       RAM_WEn <= ~write;  // Creates IOB flob
+	       
 	       
 	       if (write)
 		 data_out_pipe1 <= data_out;
@@ -68,8 +72,8 @@ module nobl_if
    // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
    assign RAM_A = address_pipe1;
    assign RAM_CENn = 1'b0;
-   assign RAM_WEn = ~write_pipe1;
-   assign RAM_CE1n = ~enable_pipe1;
+ //  assign RAM_WEn = ~write_pipe1;
+//   assign RAM_CE1n = ~enable_pipe1;
 
    //
    // Pipeline stage2