diff options
Diffstat (limited to 'usrp2/coregen')
| -rw-r--r-- | usrp2/coregen/Makefile.srcs | 4 | ||||
| -rw-r--r-- | usrp2/coregen/coregen.cgp | 22 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 6 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 |
4 files changed, 23 insertions, 15 deletions
diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs index 7b29225ca..a59696d15 100644 --- a/usrp2/coregen/Makefile.srcs +++ b/usrp2/coregen/Makefile.srcs @@ -16,4 +16,8 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_512x36_2clk_36to18.v \ +fifo_xlnx_512x36_2clk_36to18.xco \ +fifo_xlnx_512x36_2clk_18to36.v \ +fifo_xlnx_512x36_2clk_18to36.xco \ )) diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v index 1d7a5ca2a..32de19e8a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -44,6 +44,7 @@ module fifo_xlnx_512x36_2clk_18to36( rst, wr_clk, wr_en, + almost_full, dout, empty, full); @@ -55,6 +56,7 @@ input rd_en; input rst; input wr_clk; input wr_en; +output almost_full; output [35 : 0] dout; output empty; output full; @@ -73,7 +75,7 @@ output full; .C_FAMILY("spartan3"), .C_FULL_FLAGS_RST_VAL(0), .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), + .C_HAS_ALMOST_FULL(1), .C_HAS_BACKUP(0), .C_HAS_DATA_COUNT(0), .C_HAS_INT_CLK(0), @@ -128,6 +130,7 @@ output full; .RST(rst), .WR_CLK(wr_clk), .WR_EN(wr_en), + .ALMOST_FULL(almost_full), .DOUT(dout), .EMPTY(empty), .FULL(full), @@ -145,7 +148,6 @@ output full; .SRST(), .WR_RST(), .ALMOST_EMPTY(), - .ALMOST_FULL(), .DATA_COUNT(), .OVERFLOW(), .PROG_EMPTY(), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco index df97fd0e0..05ceffbe9 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Thu Jul 29 23:02:41 2010 +# Date: Fri Jul 30 20:43:00 2010 # ############################################################## # @@ -36,7 +36,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 4.4 # END Select # BEGIN Parameters CSET almost_empty_flag=false -CSET almost_full_flag=false +CSET almost_full_flag=true CSET component_name=fifo_xlnx_512x36_2clk_18to36 CSET data_count=false CSET data_count_width=10 @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 117ae77f +# CRC: 9b689ee4 |