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-rw-r--r--usrp2/coregen/coregen.cgp22
1 files changed, 12 insertions, 10 deletions
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp
index 810d64dac..4c9201aff 100644
--- a/usrp2/coregen/coregen.cgp
+++ b/usrp2/coregen/coregen.cgp
@@ -1,20 +1,22 @@
-# Date: Thu Sep 3 17:40:48 2009
-SET addpads = False
-SET asysymbol = False
+# Date: Mon Jul 26 21:55:33 2010
+
+SET addpads = false
+SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
+SET createndf = false
SET designentry = Verilog
SET device = xc3s2000
SET devicefamily = spartan3
SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
+SET formalverification = false
+SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg456
-SET removerpms = False
+SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-SET workingdirectory = /home/matt/coregen/tmp
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = /tmp/
+# CRC: 394da717