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-rw-r--r--usrp2/control_lib/nsgpio16LE.v124
-rw-r--r--usrp2/control_lib/ram_2port_mixed_width.v120
-rw-r--r--usrp2/control_lib/settings_bus_16LE.v54
-rw-r--r--usrp2/control_lib/simple_uart.v13
4 files changed, 305 insertions, 6 deletions
diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..6847bb4a9
--- /dev/null
+++ b/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,124 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// OpenCores Simple General Purpose IO core ////
+//// ////
+//// Author: Richard Herveille ////
+//// richard@asics.ws ////
+//// www.asics.ws ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2002 Richard Herveille ////
+//// richard@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+ (input clk_i, input rst_i,
+ input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i,
+ output reg [15:0] dat_o, output reg ack_o,
+ input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1,
+ inout [31:0] gpio
+ );
+
+ reg [63:0] ctrl;
+ reg [31:0] line;
+ reg [31:0] lgpio; // LatchedGPIO pins
+ reg [31:0] ddr;
+
+ wire wb_acc = cyc_i & stb_i; // WISHBONE access
+ wire wb_wr = wb_acc & we_i; // WISHBONE write access
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ begin
+ ctrl <= 64'h0;
+ line <= 0;
+ end
+ else if (wb_wr)
+ case( adr_i[3:1] )
+ 3'b000 :
+ line[15:0] <= dat_i;
+ 3'b001 :
+ line[31:16] <= dat_i;
+ 3'b010 :
+ ddr[15:0] <= dat_i;
+ 3'b011 :
+ ddr[31:16] <= dat_i;
+ 3'b100 :
+ ctrl[15:0] <= dat_i;
+ 3'b101 :
+ ctrl[31:16] <= dat_i;
+ 3'b110 :
+ ctrl[47:32] <= dat_i;
+ 3'b111 :
+ ctrl[63:48] <= dat_i;
+ endcase // case ( adr_i[3:1] )
+
+ always @(posedge clk_i)
+ case (adr_i[3:1])
+ 3'b000 :
+ dat_o <= lgpio[15:0];
+ 3'b001 :
+ dat_o <= lgpio[31:16];
+ 3'b010 :
+ dat_o <= ddr[15:0];
+ 3'b011 :
+ dat_o <= ddr[31:16];
+ 3'b100 :
+ dat_o <= ctrl[15:0];
+ 3'b101 :
+ dat_o <= ctrl[31:16];
+ 3'b110 :
+ dat_o <= ctrl[47:32];
+ 3'b111 :
+ dat_o <= ctrl[63:48];
+ endcase // case (adr_i[3:1])
+
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ ack_o <= 1'b0;
+ else
+ ack_o <= wb_acc & !ack_o;
+
+ // latch GPIO input pins
+ always @(posedge clk_i)
+ lgpio <= gpio;
+
+ // assign GPIO outputs
+ integer n;
+ reg [31:0] igpio; // temporary internal signal
+
+ always @(ctrl or line or debug_1 or debug_0 or atr)
+ for(n=0;n<32;n=n+1)
+ igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) :
+ (ctrl[2*n] ? atr[n] : line[n]) )
+ : 1'bz;
+
+ assign gpio = igpio;
+
+endmodule
+
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+ (input clk16,
+ input en16,
+ input we16,
+ input [10:0] addr16,
+ input [15:0] di16,
+ output [15:0] do16,
+ input clk32,
+ input en32,
+ input we32,
+ input [9:0] addr32,
+ input [31:0] di32,
+ output [31:0] do32);
+
+ wire en32a = en32 & ~addr32[9];
+ wire en32b = en32 & addr32[9];
+ wire en16a = en16 & ~addr16[10];
+ wire en16b = en16 & addr16[10];
+
+ wire [31:0] do32a, do32b;
+ wire [15:0] do16a, do16b;
+
+ assign do32 = addr32[9] ? do32b : do32a;
+ assign do16 = addr16[10] ? do16b : do16a;
+
+ RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+ .INIT_B(18'h00000),
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(18'h00000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ )
+ RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output
+ .DOB(do16a), // Port B 16-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .DOPB(), // Port B 2-bit Parity Output
+ .ADDRA(addr32[8:0]), // Port A 9-bit Address Input
+ .ADDRB(addr16[9:0]), // Port B 10-bit Address Input
+ .CLKA(clk32), // Port A 1-bit Clock
+ .CLKB(clk16), // Port B 1-bit Clock
+ .DIA(di32), // Port A 32-bit Data Input
+ .DIB(di16), // Port B 16-bit Data Input
+ .DIPA(0), // Port A 4-bit parity Input
+ .DIPB(0), // Port-B 2-bit parity Input
+ .ENA(en32a), // Port A 1-bit RAM Enable Input
+ .ENB(en16a), // Port B 1-bit RAM Enable Input
+ .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input
+ .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEA({4{we32}}), // Port A 4-bit Write Enable Input
+ .WEB({2{we16}}) // Port B 2-bit Write Enable Input
+ );
+
+ RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+ .INIT_B(18'h00000),
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(18'h00000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ )
+ RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output
+ .DOB(do16b), // Port B 16-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .DOPB(), // Port B 2-bit Parity Output
+ .ADDRA(addr32[8:0]), // Port A 9-bit Address Input
+ .ADDRB(addr16[9:0]), // Port B 10-bit Address Input
+ .CLKA(clk32), // Port A 1-bit Clock
+ .CLKB(clk16), // Port B 1-bit Clock
+ .DIA(di32), // Port A 32-bit Data Input
+ .DIB(di16), // Port B 16-bit Data Input
+ .DIPA(0), // Port A 4-bit parity Input
+ .DIPB(0), // Port-B 2-bit parity Input
+ .ENA(en32b), // Port A 1-bit RAM Enable Input
+ .ENB(en16b), // Port B 1-bit RAM Enable Input
+ .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input
+ .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEA({4{we32}}), // Port A 4-bit Write Enable Input
+ .WEB({2{we16}}) // Port B 2-bit Write Enable Input
+ );
+
+endmodule // ram_2port_mixed_width
+
+
+
+
+// ISE 10.1.03 chokes on the following
+
+/*
+
+ reg [31:0] ram [(1<<AWIDTH)-1:0];
+ integer i;
+ initial
+ for(i=0;i<512;i=i+1)
+ ram[i] <= 32'b0;
+
+ always @(posedge clk16)
+ if (en16)
+ begin
+ if (we16)
+ if(addr16[0])
+ ram[addr16[10:1]][15:0] <= di16;
+ else
+ ram[addr16[10:1]][31:16] <= di16;
+ do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+ end
+
+ always @(posedge clk32)
+ if (en32)
+ begin
+ if (we32)
+ ram[addr32] <= di32;
+ do32 <= ram[addr32];
+ end
+
+endmodule // ram_2port_mixed_width
+
+
+ */
diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..fbef9b1c9
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+ #(parameter AWIDTH=16)
+ (input wb_clk,
+ input wb_rst,
+ input [AWIDTH-1:0] wb_adr_i,
+ input [15:0] wb_dat_i,
+ input wb_stb_i,
+ input wb_we_i,
+ output reg wb_ack_o,
+ output strobe,
+ output reg [7:0] addr,
+ output reg [31:0] data);
+
+ reg stb_int;
+
+ always @(posedge wb_clk)
+ if(wb_rst)
+ begin
+ stb_int <= 1'b0;
+ addr <= 8'd0;
+ data <= 32'd0;
+ end
+ else if(wb_we_i & wb_stb_i)
+ begin
+ addr <= wb_adr_i[9:2];
+ if(wb_adr_i[1])
+ begin
+ stb_int <= 1'b1; // We now have both halves
+ data[31:16] <= wb_dat_i;
+ end
+ else
+ begin
+ stb_int <= 1'b0; // Don't strobe, we need other half
+ data[15:0] <= wb_dat_i;
+ end
+ end
+ else
+ stb_int <= 1'b0;
+
+ always @(posedge wb_clk)
+ if(wb_rst)
+ wb_ack_o <= 0;
+ else
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+ assign strobe = stb_int & wb_ack_o;
+
+endmodule // settings_bus_16LE
diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/usrp2/control_lib/simple_uart.v
+++ b/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
module simple_uart
#(parameter TXDEPTH = 1,
- parameter RXDEPTH = 1)
- (input clk_i, input rst_i,
- input we_i, input stb_i, input cyc_i, output reg ack_o,
- input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
- output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+ parameter RXDEPTH = 1,
+ parameter CLKDIV_DEFAULT = 16'd0)
+ (input clk_i, input rst_i,
+ input we_i, input stb_i, input cyc_i, output reg ack_o,
+ input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+ output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
// Register Map
localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
always @(posedge clk_i)
if (rst_i)
- clkdiv <= 0;
+ clkdiv <= CLKDIV_DEFAULT;
else if (wb_wr)
case(adr_i)
SUART_CLKDIV : clkdiv <= dat_i[15:0];
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-19 12:05:17 +0000