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-rw-r--r--usrp2/control_lib/atr_controller.v2
-rw-r--r--usrp2/control_lib/atr_controller16.v2
2 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v
index 1f8d75d00..ee8b260c5 100644
--- a/usrp2/control_lib/atr_controller.v
+++ b/usrp2/control_lib/atr_controller.v
@@ -47,7 +47,7 @@ module atr_controller
// Removing readback allows ram to be synthesized as LUTs instead of regs
//always @(posedge clk_i)
// dat_o <= atr_ram[adr_i[5:2]];
- always @*
+ always
dat_o <= 32'd0;
always @(posedge clk_i)
diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
index a2ebd1dde..727f8c630 100644
--- a/usrp2/control_lib/atr_controller16.v
+++ b/usrp2/control_lib/atr_controller16.v
@@ -50,7 +50,7 @@ module atr_controller16
// Removing readback allows ram to be synthesized as LUTs instead of regs
//always @(posedge clk_i)
// dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
- always @*
+ always
dat_o <= 16'd0;
always @(posedge clk_i)