diff options
Diffstat (limited to 'usrp2/control_lib')
| -rw-r--r-- | usrp2/control_lib/atr_controller16.v | 60 | ||||
| -rw-r--r-- | usrp2/control_lib/nsgpio16LE.v | 23 | ||||
| -rw-r--r-- | usrp2/control_lib/settings_bus_16LE.v | 4 |
3 files changed, 73 insertions, 14 deletions
diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v new file mode 100644 index 000000000..3d8b5b1e9 --- /dev/null +++ b/usrp2/control_lib/atr_controller16.v @@ -0,0 +1,60 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller16 + (input clk_i, input rst_i, + input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), + (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_int[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; + if(sel_int[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; + if(sel_int[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_int[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller16 diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index 6847bb4a9..d6d7dcf56 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -43,10 +43,7 @@ module nsgpio16LE inout [31:0] gpio ); - reg [63:0] ctrl; - reg [31:0] line; - reg [31:0] lgpio; // LatchedGPIO pins - reg [31:0] ddr; + reg [31:0] ctrl, line, ddr, dbg, lgpio; wire wb_acc = cyc_i & stb_i; // WISHBONE access wire wb_wr = wb_acc & we_i; // WISHBONE write access @@ -54,8 +51,10 @@ module nsgpio16LE always @(posedge clk_i or posedge rst_i) if (rst_i) begin - ctrl <= 64'h0; - line <= 0; + ctrl <= 32'h0; + line <= 32'h0; + ddr <= 32'h0; + dbg <= 32'h0; end else if (wb_wr) case( adr_i[3:1] ) @@ -72,9 +71,9 @@ module nsgpio16LE 3'b101 : ctrl[31:16] <= dat_i; 3'b110 : - ctrl[47:32] <= dat_i; + dbg[15:0] <= dat_i; 3'b111 : - ctrl[63:48] <= dat_i; + dbg[31:16] <= dat_i; endcase // case ( adr_i[3:1] ) always @(posedge clk_i) @@ -92,9 +91,9 @@ module nsgpio16LE 3'b101 : dat_o <= ctrl[31:16]; 3'b110 : - dat_o <= ctrl[47:32]; + dat_o <= dbg[15:0]; 3'b111 : - dat_o <= ctrl[63:48]; + dat_o <= dbg[31:16]; endcase // case (adr_i[3:1]) @@ -114,8 +113,8 @@ module nsgpio16LE always @(ctrl or line or debug_1 or debug_0 or atr) for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : - (ctrl[2*n] ? atr[n] : line[n]) ) + igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : + (ctrl[n] ? atr[n] : line[n]) ) : 1'bz; assign gpio = igpio; diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v index fbef9b1c9..76061e9e0 100644 --- a/usrp2/control_lib/settings_bus_16LE.v +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -5,7 +5,7 @@ // The setting regs are strobed when the high 16 bits are written module settings_bus_16LE - #(parameter AWIDTH=16) + #(parameter AWIDTH=16, RWIDTH=8) (input wb_clk, input wb_rst, input [AWIDTH-1:0] wb_adr_i, @@ -28,7 +28,7 @@ module settings_bus_16LE end else if(wb_we_i & wb_stb_i) begin - addr <= wb_adr_i[9:2]; + addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits if(wb_adr_i[1]) begin stb_int <= 1'b1; // We now have both halves |