12 files changed, 568 insertions, 56 deletions

diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/usrp2/control_lib/newfifo/.gitignore
+++ b/usrp2/control_lib/newfifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
 a.out
diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..5f9aeff9b 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
 
    output [35:0] f36_dataout,
    output f36_src_rdy_o,
-   input f36_dst_rdy_i
+   input f36_dst_rdy_i,
+   output [31:0] debug
    );
 
    reg 	 f36_sof, f36_eof, f36_occ;
@@ -50,7 +51,9 @@ module fifo19_to_fifo36
 	     state <= 2;
 	   2 : 
 	     if(xfer_out)
-	       state 	   <= 1;
+	       if(~f19_eof)
+		 state 	   <= 1;
+	   // remain in state 2 if we are at eof
 	 endcase // case(state)
        else
 	 if(xfer_out)
@@ -67,5 +70,7 @@ module fifo19_to_fifo36
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
    assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
-      
+
+   assign    debug = state;
+   
 endmodule // fifo19_to_fifo36
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
index c65be5136..af3b91afb 100644
--- a/usrp2/control_lib/newfifo/ll8_to_fifo19.v
+++ b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
@@ -10,68 +10,64 @@ module ll8_to_fifo19
    output [18:0] f19_data,
    output f19_src_rdy_o,
    input f19_dst_rdy_i );
-
+   
+   localparam XFER_EMPTY       = 0;
+   localparam XFER_HALF        = 1;
+   localparam XFER_HALF_WRITE  = 3;
+   
    // Why anybody would use active low in an FPGA is beyond me...
    wire  ll_sof      = ~ll_sof_n;
    wire  ll_eof      = ~ll_eof_n;
    wire  ll_src_rdy  = ~ll_src_rdy_n;
    wire  ll_dst_rdy;
    assign    ll_dst_rdy_n  = ~ll_dst_rdy;
-
-   wire xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   //  wire xfer_in 	   = ll_src_rdy & ll_dst_rdy;   Not needed
    
-   reg 	 f19_sof, f19_eof, f19_occ;
+   wire  xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire  xfer_in 	   = ll_src_rdy & ll_dst_rdy; 
+   
+   reg 	 hold_sof;
+   wire  f19_sof, f19_eof, f19_occ;
    
    reg [1:0] state;
-   reg [7:0] dat0, dat1;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0)|xfer_out))
-       f19_sof <= ll_sof;
-
+   reg [7:0] hold_reg;
+   
    always @(posedge clk)
-     if(ll_src_rdy & ((state != 2)|xfer_out))
-       f19_eof <= ll_eof;
-
+     if(ll_src_rdy & (state==XFER_EMPTY))
+       hold_reg 	      <= ll_data;
+   
    always @(posedge clk)
-     if(ll_eof)
-       f19_occ <= ~state[0];
-     else
-       f19_occ <= 0;
+     if(ll_sof & (state==XFER_EMPTY))
+       hold_sof 	      <= 1;
+     else if(xfer_out)
+       hold_sof 	      <= 0;
    
    always @(posedge clk)
-     if(reset)
-       state   <= 0;
+     if(reset | clear)
+       state 		      <= XFER_EMPTY;
      else
-       if(ll_src_rdy)
-	 case(state)
-	   0 : 
+       case(state)
+	 XFER_EMPTY :
+	   if(ll_src_rdy)
 	     if(ll_eof)
-	       state <= 2;
+	       state 	      <= XFER_HALF_WRITE;
 	     else
-	       state <= 1;
-	   1 : 
-	     state <= 2;
-	   2 : 
-	     if(xfer_out)
-	       state 	   <= 1;
-	 endcase // case(state)
-       else
-	 if(xfer_out)
-	   state 	   <= 0;
-
-   always @(posedge clk)
-     if(ll_src_rdy & (state==1))
-       dat1 		   <= ll_data;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0) | xfer_out))
-       dat0 		   <= ll_data;
+	       state 	      <= XFER_HALF;
+	 XFER_HALF :
+	   if(ll_src_rdy & f19_dst_rdy_i)
+	       state 	      <= XFER_EMPTY;
+         XFER_HALF_WRITE :
+	   if(f19_dst_rdy_i)
+	     state 	<= XFER_EMPTY;
+       endcase // case (state)
+      
+   assign ll_dst_rdy 	 = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+   
+   assign f19_sof 	 = hold_sof | (ll_sof & (state==XFER_HALF));
+   assign f19_eof 	 = (state == XFER_HALF_WRITE) | ll_eof;
+   assign f19_occ 	 = (state == XFER_HALF_WRITE);
    
-   assign    ll_dst_rdy     = xfer_out | (state != 2);
-   assign    f19_data 	    = {f19_occ,f19_eof,f19_sof,dat0,dat1};
-   assign    f19_src_rdy_o  = (state == 2);
+   assign f19_data 	 = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
       
 endmodule // ll8_to_fifo19
 
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..e5bfe5b26
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd100;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..22c924198
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,63 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   assign dst_rdy_o = ~last_byte_d1;
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..d6d7dcf56
--- /dev/null
+++ b/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,123 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, 
+   output reg [15:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:1] )
+	 3'b000 : 
+           line[15:0] <= dat_i;
+	 3'b001 : 
+           line[31:16] <= dat_i;
+	 3'b010 :
+	   ddr[15:0] <= dat_i;
+	 3'b011 :
+	   ddr[31:16] <= dat_i;
+	 3'b100 :
+	   ctrl[15:0] <= dat_i;
+	 3'b101 :
+	   ctrl[31:16] <= dat_i;
+	 3'b110 :
+	   dbg[15:0] <= dat_i;
+	 3'b111 :
+	   dbg[31:16] <= dat_i;
+       endcase // case ( adr_i[3:1] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:1])
+       3'b000 :
+	 dat_o <= lgpio[15:0];
+       3'b001 :
+	 dat_o <= lgpio[31:16];
+       3'b010 :
+	 dat_o <= ddr[15:0];
+       3'b011 :
+	 dat_o <= ddr[31:16];
+       3'b100 :
+	 dat_o <= ctrl[15:0];
+       3'b101 :
+	 dat_o <= ctrl[31:16];
+       3'b110 :
+	 dat_o <= dbg[15:0];
+       3'b111 :
+	 dat_o <= dbg[31:16];
+     endcase // case (adr_i[3:1])
+   
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+  (input clk16,
+   input en16,
+   input we16,
+   input [10:0] addr16,
+   input [15:0] di16,
+   output [15:0] do16,
+   input clk32,
+   input en32,
+   input we32,
+   input [9:0] addr32,
+   input [31:0] di32,
+   output [31:0] do32);
+
+   wire 	 en32a = en32 & ~addr32[9];
+   wire 	 en32b = en32 & addr32[9];
+   wire 	 en16a = en16 & ~addr16[10];
+   wire 	 en16b = en16 & addr16[10];
+
+   wire [31:0] 	 do32a, do32b;
+   wire [15:0] 	 do16a, do16b;
+   
+   assign do32 = addr32[9] ? do32b : do32a;
+   assign do16 = addr16[10] ? do16b : do16a;
+   
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_0 (.DOA(do32a),       // Port A 32-bit Data Output
+			.DOB(do16a),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32a),       // Port A 1-bit RAM Enable Input
+			.ENB(en16a),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_1 (.DOA(do32b),       // Port A 32-bit Data Output
+			.DOB(do16b),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32b),       // Port A 1-bit RAM Enable Input
+			.ENB(en16b),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
+   
+   reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
+   integer 	       i;
+   initial
+     for(i=0;i<512;i=i+1)
+       ram[i] <= 32'b0;
+   
+   always @(posedge clk16)
+     if (en16)
+       begin
+          if (we16)
+            if(addr16[0])
+	      ram[addr16[10:1]][15:0] <= di16;
+	    else
+	      ram[addr16[10:1]][31:16] <= di16;
+	  do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+       end
+
+   always @(posedge clk32)
+     if (en32)
+       begin
+          if (we32)
+            ram[addr32] <= di32;
+          do32 <= ram[addr32];
+       end
+
+endmodule // ram_2port_mixed_width
+
+ 
+ */
diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v
index ccbaa3d2e..c8aff230f 100644
--- a/usrp2/control_lib/setting_reg.v
+++ b/usrp2/control_lib/setting_reg.v
@@ -1,14 +1,14 @@
 
 
 module setting_reg
-  #(parameter my_addr = 0)
+  #(parameter my_addr = 0, parameter at_reset=32'd0)
     (input clk, input rst, input strobe, input wire [7:0] addr,
      input wire [31:0] in, output reg [31:0] out, output reg changed);
    
    always @(posedge clk)
      if(rst)
        begin
-	  out <= 32'd0;
+	  out <= at_reset;
 	  changed <= 1'b0;
        end
      else
diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE
diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/usrp2/control_lib/simple_uart.v
+++ b/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
 
 module simple_uart
   #(parameter TXDEPTH = 1,
-    parameter RXDEPTH = 1)
-    (input clk_i, input rst_i,
-     input we_i, input stb_i, input cyc_i, output reg ack_o,
-     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+    parameter RXDEPTH = 1,
+    parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
    
    // Register Map
    localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
    
    always @(posedge clk_i)
      if (rst_i)
-       clkdiv <= 0;
+       clkdiv <= CLKDIV_DEFAULT;
      else if (wb_wr)
        case(adr_i)
 	 SUART_CLKDIV : clkdiv <= dat_i[15:0];