16 files changed, 940 insertions, 230 deletions

diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index 5e2a96a53..095890d59 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -41,4 +41,7 @@ pic.v \
 longfifo.v \
 shortfifo.v \
 medfifo.v \
+nsgpio16LE.v \
+settings_bus_16LE.v \
+atr_controller16.v \
 ))
diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v
new file mode 100644
index 000000000..1bf03ab6e
--- /dev/null
+++ b/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+  (input clk,
+   input reset,
+   input [7:0] rate,
+   input enable,
+   input src1_rdy_i, output dst1_rdy_o,
+   output src2_rdy_o, input dst2_rdy_i,
+   output underrun, overrun);
+
+   wire   strobe;
+   
+   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+   wire   all_ready = src1_rdy_i & dst2_rdy_i;
+   assign dst1_rdy_o = all_ready & strobe;
+   assign src2_rdy_o = dst1_rdy_o;
+
+   assign underrun = strobe & ~src1_rdy_i;
+   assign overrun = strobe & ~dst2_rdy_i;
+   
+endmodule // fifo_pacer
diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v
new file mode 100644
index 000000000..82bb09c29
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet32_tb.v
@@ -0,0 +1,27 @@
+
+
+module packet32_tb();
+
+   wire [35:0] data;
+   wire       src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet32_tb.vcd");
+   initial $dumpvars(0,packet32_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet32_tb
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..6e8b45ccd
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd2000;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..b49ad1bbb
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,61 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..06a13d242
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,30 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   wire [35:0] 	     data_int;
+   wire 	     src_rdy_int, dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..8aef0c7ae
--- /dev/null
+++ b/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,123 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, 
+   output reg [15:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:1] )
+	 3'b000 : 
+           line[15:0] <= dat_i;
+	 3'b001 : 
+           line[31:16] <= dat_i;
+	 3'b010 :
+	   ddr[15:0] <= dat_i;
+	 3'b011 :
+	   ddr[31:16] <= dat_i;
+	 3'b100 :
+	   ctrl[15:0] <= dat_i;
+	 3'b101 :
+	   ctrl[31:16] <= dat_i;
+	 3'b110 :
+	   dbg[15:0] <= dat_i;
+	 3'b111 :
+	   dbg[31:16] <= dat_i;
+       endcase // case ( adr_i[3:1] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:1])
+       3'b000 :
+	 dat_o <= lgpio[15:0];
+       3'b001 :
+	 dat_o <= lgpio[31:16];
+       3'b010 :
+	 dat_o <= ddr[15:0];
+       3'b011 :
+	 dat_o <= ddr[31:16];
+       3'b100 :
+	 dat_o <= ctrl[15:0];
+       3'b101 :
+	 dat_o <= ctrl[31:16];
+       3'b110 :
+	 dat_o <= dbg[15:0];
+       3'b111 :
+	 dat_o <= dbg[31:16];
+     endcase // case (adr_i[3:1])
+   
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+  (input clk16,
+   input en16,
+   input we16,
+   input [10:0] addr16,
+   input [15:0] di16,
+   output [15:0] do16,
+   input clk32,
+   input en32,
+   input we32,
+   input [9:0] addr32,
+   input [31:0] di32,
+   output [31:0] do32);
+
+   wire 	 en32a = en32 & ~addr32[9];
+   wire 	 en32b = en32 & addr32[9];
+   wire 	 en16a = en16 & ~addr16[10];
+   wire 	 en16b = en16 & addr16[10];
+
+   wire [31:0] 	 do32a, do32b;
+   wire [15:0] 	 do16a, do16b;
+   
+   assign do32 = addr32[9] ? do32b : do32a;
+   assign do16 = addr16[10] ? do16b : do16a;
+   
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_0 (.DOA(do32a),       // Port A 32-bit Data Output
+			.DOB(do16a),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32a),       // Port A 1-bit RAM Enable Input
+			.ENB(en16a),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_1 (.DOA(do32b),       // Port A 32-bit Data Output
+			.DOB(do16b),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32b),       // Port A 1-bit RAM Enable Input
+			.ENB(en16b),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
+   
+   reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
+   integer 	       i;
+   initial
+     for(i=0;i<512;i=i+1)
+       ram[i] <= 32'b0;
+   
+   always @(posedge clk16)
+     if (en16)
+       begin
+          if (we16)
+            if(addr16[0])
+	      ram[addr16[10:1]][15:0] <= di16;
+	    else
+	      ram[addr16[10:1]][31:16] <= di16;
+	  do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+       end
+
+   always @(posedge clk32)
+     if (en32)
+       begin
+          if (we32)
+            ram[addr32] <= di32;
+          do32 <= ram[addr32];
+       end
+
+endmodule // ram_2port_mixed_width
+
+ 
+ */
diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v
new file mode 100644
index 000000000..948f9b36f
--- /dev/null
+++ b/usrp2/control_lib/ram_harvard.v
@@ -0,0 +1,69 @@
+
+
+// Dual ported, Harvard architecture, cached ram
+
+module ram_harvard
+  #(parameter AWIDTH=15,
+    parameter RAM_SIZE=16384,
+    parameter ICWIDTH=6,
+    parameter DCWIDTH=6)
+   
+    (input wb_clk_i, 
+     input wb_rst_i,
+     // Firmware download port.
+     input [AWIDTH-1:0] ram_loader_adr_i,
+     input [31:0] ram_loader_dat_i,
+     input [3:0] ram_loader_sel_i,
+     input ram_loader_stb_i,
+     input ram_loader_we_i,
+     input ram_loader_done_i,    
+     // Instruction fetch port.
+     input [AWIDTH-1:0] if_adr,
+     output [31:0] if_data,
+     // Data access port.
+     input [AWIDTH-1:0] dwb_adr_i,
+     input [31:0] dwb_dat_i, 
+     output [31:0] dwb_dat_o,
+     input dwb_we_i,
+     output dwb_ack_o,
+     input dwb_stb_i,
+     input [3:0] dwb_sel_i,
+
+     input flush_icache );
+
+   reg 	   ack_d1;
+   reg 	   stb_d1;
+   
+   dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) 
+   sys_ram
+     (.clk(wb_clk_i),
+      .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i),
+      .dat1_i(ram_loader_dat_i),
+      .dat1_o(if_data),
+      .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
+      .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i),
+      //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
+      .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway
+      .adr2_i(dwb_adr_i),
+      .dat2_i(dwb_dat_i),
+      .dat2_o(dwb_dat_o),
+      .we2_i(dwb_we_i),
+      .en2_i(dwb_stb_i),
+      .sel2_i(dwb_sel_i) 
+      );
+
+   assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= dwb_ack_o;
+
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= dwb_stb_i;
+
+endmodule // ram_harvard
diff --git a/usrp2/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v
index cb67de739..c53ea7aa7 100644
--- a/usrp2/control_lib/ram_loader.v
+++ b/usrp2/control_lib/ram_loader.v
@@ -1,225 +1,261 @@
+module ram_loader
+  #(parameter AWIDTH=16, RAM_SIZE=16384)
+    (
+     // Wishbone I/F and clock domain
+     input wb_clk,
+     input dsp_clk,
+     input ram_loader_rst,
+     output wire [31:0] wb_dat,
+     output wire [AWIDTH-1:0] wb_adr,
+     output wb_stb,
+     output reg [3:0] wb_sel,
+     output wb_we,
+     output reg ram_loader_done,
+     // CPLD signals and clock domain
+     input cpld_clk,
+     input cpld_din,
+     output reg cpld_start,
+     output reg cpld_mode,
+     output reg cpld_done,
+     input cpld_detached
+     );
 
-// Adapted from VHDL code in spi_boot by Arnim Legauer
-//  Added a full wishbone master interface (32-bit)
-
-module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384)
-  (input clk_i, input rst_i,
-   // CPLD Interface
-   input cfg_clk_i, input cfg_data_i,
-   output start_o, output mode_o, output done_o,
-   input detached_i,
-   // Wishbone interface
-   output wire [31:0] wb_dat_o,
-   output reg [AWIDTH-1:0] wb_adr_o,
-   output wb_stb_o,
-   output wb_cyc_o,
-   output reg [3:0] wb_sel_o,
-   output reg wb_we_o,
-   input wb_ack_i,
-   output ram_loader_done_o);
+   localparam S0 = 0;
+   localparam S1 = 1;
+   localparam S2 = 2;
+   localparam S3 = 3;
+   localparam S4 = 4;
+   localparam S5 = 5;
+   localparam S6 = 6;
+   localparam RESET = 7;
    
-   //  FSM to control start signal, clocked on main clock
-   localparam FSM1_WAIT_DETACH = 2'b00;
-   localparam FSM1_CHECK_NO_DONE = 2'b01;
-   localparam FSM1_WAIT_DONE = 2'b10;
-   
-   reg [1:0]  start_fsm_q, start_fsm_s;
-   reg 	      start_q, enable_q, start_s, enable_s;
-   reg 	      done_q, done_s;
+   localparam WB_IDLE = 0;
+   localparam WB_WRITE = 1;
+  
+
+   reg [AWIDTH+2:0] count;       // 3 LSB's count bits in, the MSB's generate the Wishbone address
+   reg [6:0] 	    shift_reg;
+   reg [7:0] 	    data_reg;
+   reg 		    sampled_clk;
+   reg 		    sampled_clk_meta;
+   reg 		    sampled_din;
+   reg 		    inc_count;
+   reg 		    load_data_reg;
+   reg 		    shift;  
+   reg 		    wb_state, wb_next_state;
+   reg [2:0] 	    state, next_state;
+    
+   //
+   // CPLD clock doesn't free run and is approximately 12.5MHz.
+   // Use 50MHz Wishbone clock to sample it as a signal and avoid having
+   // an extra clock domain for no reason.
+   //
+
+   always @(posedge dsp_clk or posedge ram_loader_rst)
+      if (ram_loader_rst)
+	begin
+	   sampled_clk_meta <= 1'b0;
+	   sampled_clk <= 1'b0;
+	   sampled_din <= 1'b0;
+	   count <= 'h7FFF8;  // Initialize so that address will be 0 when first byte fully received.
+	   data_reg <= 0;
+	   shift_reg <= 0;
+	end
+      else 
+	begin
+	   sampled_clk_meta <= cpld_clk;
+	   sampled_clk <= sampled_clk_meta;
+	   sampled_din <= cpld_din;
+	   if (inc_count)
+	     count <= count + 1'b1;
+	   if (load_data_reg)
+	     data_reg <= {shift_reg,sampled_din};
+	   if (shift)
+	     shift_reg <= {shift_reg[5:0],sampled_din};	   
+	end // else: !if(ram_loader_rst)
    
-   always @(posedge clk_i or posedge rst_i)
-     if(rst_i)
-       begin
-	  start_fsm_q <= FSM1_WAIT_DETACH;
-	  start_q <= 1'b0;
-	  enable_q <= 1'b0;
-       end
+	   
+   always @(posedge dsp_clk or posedge ram_loader_rst)
+     if (ram_loader_rst)
+       state <= RESET;
      else
-       begin
-	  start_fsm_q <= start_fsm_s;
-	  enable_q <= enable_s;
-	  start_q <= start_s;
-       end // else: !if(rst_i)
-   
+       state <= next_state;
+
+
    always @*
-     case(start_fsm_q)
-       FSM1_WAIT_DETACH:
-	 if(detached_i == 1'b1)
-	   begin
-	      start_fsm_s <= FSM1_CHECK_NO_DONE;
-	      enable_s <= 1'b1;
-	      start_s <= 1'b1;
-	   end
-	 else
-	   begin
-	      start_fsm_s <= FSM1_WAIT_DETACH;
-	      enable_s <= enable_q;
-	      start_s <= start_q;
-	   end // else: !if(detached_i == 1'b1)
-       FSM1_CHECK_NO_DONE:
-	 if(~done_q)
-	   begin
-	      start_fsm_s  <= FSM1_WAIT_DONE;
-	      enable_s <= enable_q;
-	      start_s <= start_q;
-	   end
-	 else
-	   begin
-	      start_fsm_s  <= FSM1_CHECK_NO_DONE;
-	      enable_s <= enable_q;
-	      start_s <= start_q;
-	   end // else: !if(~done_q)
-       FSM1_WAIT_DONE:
-	 if(done_q)
-	   begin
-	      start_fsm_s  <= FSM1_WAIT_DETACH;
-	      enable_s <= 1'b0;
-	      start_s <= 1'b0;
-	   end
-	 else
-	   begin
-	      start_fsm_s  <= FSM1_WAIT_DONE;
-	      enable_s <= enable_q;
-	      start_s <= start_q;
-	   end // else: !if(done_q)
-       default:
-	 begin
-	    start_fsm_s  <= FSM1_WAIT_DETACH;
-	    enable_s <= enable_q;
-	    start_s <= start_q;
-	 end // else: !if(done_q)
-     endcase // case(start_fsm_q)
-   
-   //  FSM running on data clock
-
-   localparam FSM2_IDLE = 3'b000;
-   localparam FSM2_WE_ON = 3'b001;
-   localparam FSM2_WE_OFF = 3'b010;
-   localparam FSM2_INC_ADDR1 = 3'b011;
-   localparam FSM2_INC_ADDR2 = 3'b100;
-   localparam FSM2_FINISHED = 3'b101;
-   
-   reg [AWIDTH-1:0] addr_q;
-   reg [7:0] 	    shift_dat_q, ser_dat_q;
-   reg [2:0] 	    bit_q, fsm_q, fsm_s;
-   reg 		    bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s;
-   
-   always @(posedge cfg_clk_i or posedge rst_i)
-     if(rst_i)
-       begin
-	  addr_q <= 0;
-	  shift_dat_q <= 8'd0;
-	  ser_dat_q <= 8'd0;
-	  bit_q <= 3'd0;
-	  bit_ovfl_q <= 1'b0;
-	  fsm_q <= FSM2_IDLE;
-	  ram_we_q <= 1'b0;
-	  done_q <= 1'b0;
-	  mode_q <= 1'b0;
-       end
+     begin
+	// Defaults
+	next_state = state;
+	cpld_start = 1'b0;
+	shift = 1'b0;
+	inc_count = 0;
+	load_data_reg = 1'b0;
+	ram_loader_done = 1'b0;
+	cpld_mode = 1'b0;
+	cpld_done = 1'b1;
+	
+	
+	
+	case (state) //synthesis parallel_case full_case
+	  // After reset wait until CPLD indicates its detached.
+	  RESET: begin		     
+	     if (cpld_detached)
+	       next_state = S0;
+	     else
+	       next_state = RESET;
+	  end
+
+	  // Assert cpld_start to signal the CPLD its to start sending serial clock and data.
+	  // Assume cpld_clk is low as we transition into search for first rising edge
+	  S0: begin
+	     cpld_start = 1'b1;	 
+	     cpld_done = 1'b0;	 
+	     if (~cpld_detached)
+	       next_state = S2;
+	     else
+	       next_state = S0;   
+	  end
+	  
+	  //
+	  S1: begin
+	     cpld_start = 1'b1;	   
+	     cpld_done = 1'b0;	 
+	     if (sampled_clk)
+	       begin
+		  // Found rising edge on cpld_clk.
+		  if (count[2:0] == 3'b111)
+		    // Its the last bit of a byte, send it out to the Wishbone bus.
+		    begin
+		       load_data_reg = 1'b1;
+		       inc_count = 1'b1;
+		    end
+		  else 
+	          // Shift databit into LSB of shift register and increment count
+		     begin
+		       shift = 1'b1;
+		       inc_count = 1'b1;
+		     end // else: !if(count[2:0] == 3'b111)
+		  next_state = S2;
+	       end // if (sampled_clk)
+	     else
+	       next_state = S1;
+	  end // case: S1
+	  
+	  //
+	  S2: begin
+	     cpld_start = 1'b1;	    
+	     cpld_done = 1'b0;
+	     if (~sampled_clk)
+	       // Found negative edge of clock
+	       if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant
+		 // All firmware now downloaded
+		 next_state = S3;
+	       else
+		 next_state = S1;
+	     else
+	       next_state = S2;
+	  end // case: S2
+	  
+	  // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done 
+	  // and that mode is now SPI mode.
+	  S3: begin
+	     if (sampled_clk)
+	       begin
+		  cpld_mode = 1'b1;
+		  cpld_done = 1'b1;
+		  next_state = S4;
+	       end
+	     else
+	       next_state = S3;	     
+	  end
+
+	  // Search for negedge of cpld_clk whilst keeping done sequence asserted.
+	  // Keep done assserted 
+	  S4: begin
+	     cpld_mode = 1'b1;
+	     cpld_done = 1'b1;
+	     if (~sampled_clk)
+	       next_state = S5;
+	     else
+	       next_state = S4;
+	  end
+
+	  // Search for posedge of cpld_clk whilst keeping done sequence asserted.
+	  S5: begin
+	     cpld_mode = 1'b1;
+	     cpld_done = 1'b1;
+	     if (sampled_clk)
+	       next_state = S6;
+	     else	      
+	       next_state = S5;	       
+	  end
+
+	  // Stay in this state until reset/power down
+	  S6: begin
+	     ram_loader_done = 1'b1;
+	     cpld_done = 1'b1;
+	     cpld_mode = 1'b1;
+	     next_state = S6;
+	  end
+
+	endcase // case(state)
+     end
+
+   always @(posedge dsp_clk or posedge ram_loader_rst)
+     if (ram_loader_rst)
+       wb_state <= WB_IDLE;
      else
-       begin
-	  if(inc_addr_s)
-	    addr_q <= addr_q + 1;
-	  if(enable_q)
-	    begin
-	       bit_q <= bit_q + 1;
-	       bit_ovfl_q <= (bit_q == 3'd7);
-	       shift_dat_q[0] <= cfg_data_i;
-	       shift_dat_q[7:1] <= shift_dat_q[6:0];
-	    end
-	  if(bit_ovfl_q)
-	    ser_dat_q <= shift_dat_q;
-
-	  fsm_q <= fsm_s;
-
-	  ram_we_q <= ram_we_s;
-
-	  if(done_s)
-	    done_q <= 1'b1;
-	  mode_q <= mode_s;
-       end // else: !if(rst_i)
+       wb_state <= wb_next_state;
 
+   reg do_write;
+   wire empty, full;
+   
    always @*
      begin
-	inc_addr_s <= 1'b0;
-	ram_we_s <= 1'b0;
-	done_s <= 1'b0;
-	fsm_s <= FSM2_IDLE;
-	mode_s <= 1'b0;
-
-	case(fsm_q)
-	  FSM2_IDLE :
-	    if(start_q)
-	      if(bit_ovfl_q)
-		fsm_s <= FSM2_WE_ON;
-	  FSM2_WE_ON:
-	    begin
-	       ram_we_s <= 1'b1;
-	       fsm_s <= FSM2_WE_OFF;
-	    end
-	  FSM2_WE_OFF:
-	    begin
-	       ram_we_s <= 1'b1;
-	       fsm_s <= FSM2_INC_ADDR1;
-	    end
-	  FSM2_INC_ADDR1:
-	    fsm_s <= FSM2_INC_ADDR2;
-	  FSM2_INC_ADDR2:
-	    if(addr_q == (RAM_SIZE-1))
-	    //if(&addr_q)
-	      begin
-		 fsm_s <= FSM2_FINISHED;
-		 done_s <= 1'b1;
-		 mode_s <= 1'b1;
-	      end
-	    else
-	      begin
-		 inc_addr_s <= 1'b1;
-		 fsm_s <= FSM2_IDLE;
-	      end // else: !if(&addr_q)
-	  FSM2_FINISHED:
-	    begin
-	       fsm_s <= FSM2_FINISHED;
-	       mode_s <= 1'b1;
-	    end
-	endcase // case(fsm_q)
+	wb_next_state = wb_state;
+	do_write = 1'b0;
+	
+	case (wb_state) //synthesis full_case parallel_case
+	  //
+	  WB_IDLE: begin
+	     if (load_data_reg)
+	       // Data reg will load ready to write wishbone @ next clock edge
+	       wb_next_state  =  WB_WRITE;
+	     else
+	       wb_next_state = WB_IDLE;
+	  end
+
+	  // Drive address and data onto wishbone.
+	  WB_WRITE: begin
+      	     do_write = 1'b1;
+	     if (~full)	       
+	       wb_next_state =  WB_IDLE;		      
+	     else
+	       wb_next_state = WB_WRITE;	       
+	  end
+
+	endcase // case(wb_state)
      end // always @ *
    
-   assign start_o = start_q;
-   assign mode_o = mode_q;
-   assign done_o = start_q ? done_q : 1'b1;
-   wire [AWIDTH-1:0] ram_addr = addr_q;
-   wire [7:0] ram_data = ser_dat_q;
-   assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
-   
-   // wishbone master, only writes
-   reg [7:0] dat_holder;
-   assign    wb_dat_o = {4{dat_holder}};
-   assign    wb_stb_o = wb_we_o;
-   assign    wb_cyc_o = wb_we_o;
+   wire [1:0] count_out;
+   wire [7:0] data_out;
+
+   fifo_xlnx_16x40_2clk crossclk
+     (.rst(ram_loader_rst),
+      .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full),
+      .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty));
+
+   assign wb_dat = {4{data_out}};
+
+   always @*
+     case(count_out[1:0]) //synthesis parallel_case full_case
+       2'b00 : wb_sel = 4'b1000;
+       2'b01 : wb_sel = 4'b0100;
+       2'b10 : wb_sel = 4'b0010;
+       2'b11 : wb_sel = 4'b0001;
+     endcase
+
+   assign wb_we = ~empty;
+   assign wb_stb = ~empty;
    
-   always @(posedge clk_i or posedge rst_i)
-     if(rst_i)
-       begin
-	  dat_holder <= 8'd0;
-	  wb_adr_o <= 0;
-	  wb_sel_o <= 4'b0000;
-	  wb_we_o <= 1'b0;
-       end
-     else if(ram_we_q)
-       begin
-	  dat_holder <= ram_data;
-	  wb_adr_o <= ram_addr;
-	  wb_we_o <= 1'b1;
-	  case(ram_addr[1:0])   // Big Endian
-	    2'b00 : wb_sel_o <= 4'b1000;
-	    2'b01 : wb_sel_o <= 4'b0100;
-	    2'b10 : wb_sel_o <= 4'b0010;
-	    2'b11 : wb_sel_o <= 4'b0001;
-	  endcase // case(ram_addr[1:0])
-       end // if (ram_we_q)
-     else if(wb_ack_i)
-       wb_we_o <= 1'b0;
-      
 endmodule // ram_loader
diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index fc960e456..aec179516 100644
--- a/usrp2/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,7 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     output strobe,
+     output reg strobe,
      output reg [7:0] addr,
      output reg [31:0] data);
 
@@ -19,18 +19,18 @@ module settings_bus
    always @(posedge wb_clk)
      if(wb_rst)
        begin
-	  stb_int <= 1'b0;
+	  strobe <= 1'b0;
 	  addr <= 8'd0;
 	  data <= 32'd0;
        end
-     else if(wb_we_i & wb_stb_i)
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
        begin
-	  stb_int <= 1'b1;
+	  strobe <= 1'b1;
 	  addr <= wb_adr_i[9:2];
 	  data <= wb_dat_i;
        end
      else
-       stb_int <= 1'b0;
+       strobe <= 1'b0;
 
    always @(posedge wb_clk)
      if(wb_rst)
@@ -38,11 +38,4 @@ module settings_bus
      else
        wb_ack_o <= wb_stb_i & ~wb_ack_o;
 
-   always @(posedge wb_clk)
-     stb_int_d1 <= stb_int;
-
-   //assign strobe = stb_int & ~stb_int_d1;
-   assign strobe = stb_int & wb_ack_o;
-          
 endmodule // settings_bus
-
diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE
diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/usrp2/control_lib/simple_uart.v
+++ b/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
 
 module simple_uart
   #(parameter TXDEPTH = 1,
-    parameter RXDEPTH = 1)
-    (input clk_i, input rst_i,
-     input we_i, input stb_i, input cyc_i, output reg ack_o,
-     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+    parameter RXDEPTH = 1,
+    parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
    
    // Register Map
    localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
    
    always @(posedge clk_i)
      if (rst_i)
-       clkdiv <= 0;
+       clkdiv <= CLKDIV_DEFAULT;
      else if (wb_wr)
        case(adr_i)
 	 SUART_CLKDIV : clkdiv <= dat_i[15:0];