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-rw-r--r--usrp2/control_lib/wb_ram_block.v36
1 files changed, 36 insertions, 0 deletions
diff --git a/usrp2/control_lib/wb_ram_block.v b/usrp2/control_lib/wb_ram_block.v
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+++ b/usrp2/control_lib/wb_ram_block.v
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+
+
+// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency
+// These have to be a multiple of 512 lines (2K) long
+
+module wb_ram_block
+ #(parameter AWIDTH=9)
+ (input clk_i,
+ input stb_i,
+ input we_i,
+ input [AWIDTH-1:0] adr_i,
+ input [31:0] dat_i,
+ output reg [31:0] dat_o,
+ output ack_o);
+
+ reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+ always @(posedge clk_i)
+ begin
+ if(stb_i & we_i)
+ distram[adr_i] <= dat_i;
+ dat_o <= distram[adr_i];
+ end
+
+ reg stb_d1, ack_d1;
+ always @(posedge clk_i)
+ stb_d1 <= stb_i;
+
+ always @(posedge clk_i)
+ ack_d1 <= ack_o;
+
+ assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1));
+endmodule // wb_ram_block
+
+
+