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-rw-r--r--usrp2/control_lib/newfifo/.gitignore2
-rw-r--r--usrp2/control_lib/newfifo/fifo19_to_fifo36.v11
-rw-r--r--usrp2/control_lib/newfifo/ll8_to_fifo19.v86
-rw-r--r--usrp2/control_lib/newfifo/packet_generator.v59
-rw-r--r--usrp2/control_lib/newfifo/packet_tb.v29
-rw-r--r--usrp2/control_lib/newfifo/packet_verifier.v63
6 files changed, 202 insertions, 48 deletions
diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/usrp2/control_lib/newfifo/.gitignore
+++ b/usrp2/control_lib/newfifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
a.out
diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..5f9aeff9b 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
output [35:0] f36_dataout,
output f36_src_rdy_o,
- input f36_dst_rdy_i
+ input f36_dst_rdy_i,
+ output [31:0] debug
);
reg f36_sof, f36_eof, f36_occ;
@@ -50,7 +51,9 @@ module fifo19_to_fifo36
state <= 2;
2 :
if(xfer_out)
- state <= 1;
+ if(~f19_eof)
+ state <= 1;
+ // remain in state 2 if we are at eof
endcase // case(state)
else
if(xfer_out)
@@ -67,5 +70,7 @@ module fifo19_to_fifo36
assign f19_dst_rdy_o = xfer_out | (state != 2);
assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
assign f36_src_rdy_o = (state == 2);
-
+
+ assign debug = state;
+
endmodule // fifo19_to_fifo36
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
index c65be5136..af3b91afb 100644
--- a/usrp2/control_lib/newfifo/ll8_to_fifo19.v
+++ b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
@@ -10,68 +10,64 @@ module ll8_to_fifo19
output [18:0] f19_data,
output f19_src_rdy_o,
input f19_dst_rdy_i );
-
+
+ localparam XFER_EMPTY = 0;
+ localparam XFER_HALF = 1;
+ localparam XFER_HALF_WRITE = 3;
+
// Why anybody would use active low in an FPGA is beyond me...
wire ll_sof = ~ll_sof_n;
wire ll_eof = ~ll_eof_n;
wire ll_src_rdy = ~ll_src_rdy_n;
wire ll_dst_rdy;
assign ll_dst_rdy_n = ~ll_dst_rdy;
-
- wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i;
- // wire xfer_in = ll_src_rdy & ll_dst_rdy; Not needed
- reg f19_sof, f19_eof, f19_occ;
+ wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i;
+ wire xfer_in = ll_src_rdy & ll_dst_rdy;
+
+ reg hold_sof;
+ wire f19_sof, f19_eof, f19_occ;
reg [1:0] state;
- reg [7:0] dat0, dat1;
-
- always @(posedge clk)
- if(ll_src_rdy & ((state==0)|xfer_out))
- f19_sof <= ll_sof;
-
+ reg [7:0] hold_reg;
+
always @(posedge clk)
- if(ll_src_rdy & ((state != 2)|xfer_out))
- f19_eof <= ll_eof;
-
+ if(ll_src_rdy & (state==XFER_EMPTY))
+ hold_reg <= ll_data;
+
always @(posedge clk)
- if(ll_eof)
- f19_occ <= ~state[0];
- else
- f19_occ <= 0;
+ if(ll_sof & (state==XFER_EMPTY))
+ hold_sof <= 1;
+ else if(xfer_out)
+ hold_sof <= 0;
always @(posedge clk)
- if(reset)
- state <= 0;
+ if(reset | clear)
+ state <= XFER_EMPTY;
else
- if(ll_src_rdy)
- case(state)
- 0 :
+ case(state)
+ XFER_EMPTY :
+ if(ll_src_rdy)
if(ll_eof)
- state <= 2;
+ state <= XFER_HALF_WRITE;
else
- state <= 1;
- 1 :
- state <= 2;
- 2 :
- if(xfer_out)
- state <= 1;
- endcase // case(state)
- else
- if(xfer_out)
- state <= 0;
-
- always @(posedge clk)
- if(ll_src_rdy & (state==1))
- dat1 <= ll_data;
-
- always @(posedge clk)
- if(ll_src_rdy & ((state==0) | xfer_out))
- dat0 <= ll_data;
+ state <= XFER_HALF;
+ XFER_HALF :
+ if(ll_src_rdy & f19_dst_rdy_i)
+ state <= XFER_EMPTY;
+ XFER_HALF_WRITE :
+ if(f19_dst_rdy_i)
+ state <= XFER_EMPTY;
+ endcase // case (state)
+
+ assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+ assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+
+ assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF));
+ assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof;
+ assign f19_occ = (state == XFER_HALF_WRITE);
- assign ll_dst_rdy = xfer_out | (state != 2);
- assign f19_data = {f19_occ,f19_eof,f19_sof,dat0,dat1};
- assign f19_src_rdy_o = (state == 2);
+ assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
endmodule // ll8_to_fifo19
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..e5bfe5b26
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+ (input clk, input reset, input clear,
+ output reg [7:0] data_o, output sof_o, output eof_o,
+ output src_rdy_o, input dst_rdy_i);
+
+ localparam len = 32'd100;
+
+ reg [31:0] state;
+ reg [31:0] seq;
+ wire [31:0] crc_out;
+ wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+
+
+ always @(posedge clk)
+ if(reset | clear)
+ seq <= 0;
+ else
+ if(eof_o & src_rdy_o & dst_rdy_i)
+ seq <= seq + 1;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= 0;
+ else
+ if(src_rdy_o & dst_rdy_i)
+ if(state == (len - 1))
+ state <= 32'hFFFF_FFFC;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : data_o <= len[7:0];
+ 1 : data_o <= len[15:8];
+ 2 : data_o <= len[23:16];
+ 3 : data_o <= len[31:24];
+ 4 : data_o <= seq[7:0];
+ 5 : data_o <= seq[15:8];
+ 6 : data_o <= seq[23:16];
+ 7 : data_o <= seq[31:24];
+ 32'hFFFF_FFFC : data_o <= crc_out[31:24];
+ 32'hFFFF_FFFD : data_o <= crc_out[23:16];
+ 32'hFFFF_FFFE : data_o <= crc_out[15:8];
+ 32'hFFFF_FFFF : data_o <= crc_out[7:0];
+ default : data_o <= state[7:0];
+ endcase // case (state)
+
+ assign src_rdy_o = 1;
+ assign sof_o = (state == 0);
+ assign eof_o = (state == 32'hFFFF_FFFF);
+
+ wire clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+
+ crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o),
+ .calc(calc_crc), .crc_out(crc_out), .match());
+
+endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+ wire [7:0] data;
+ wire sof, eof, src_rdy, dst_rdy;
+
+ wire clear = 0;
+ reg clk = 0;
+ reg reset = 1;
+
+ always #10 clk <= ~clk;
+ initial #1000 reset <= 0;
+
+ initial $dumpfile("packet_tb.vcd");
+ initial $dumpvars(0,packet_tb);
+
+ wire [31:0] total, crc_err, seq_err, len_err;
+
+ packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+ .data_o(data), .sof_o(sof), .eof_o(eof),
+ .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+ packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+ .data_i(data), .sof_i(sof), .eof_i(eof),
+ .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+ .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..22c924198
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,63 @@
+
+
+// Packet format --
+// Line 1 -- Length, 32 bits
+// Line 2 -- Sequence number, 32 bits
+// Last line -- CRC, 32 bits
+
+module packet_verifier
+ (input clk, input reset, input clear,
+ input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o,
+
+ output reg [31:0] total,
+ output reg [31:0] crc_err,
+ output reg [31:0] seq_err,
+ output reg [31:0] len_err);
+
+ assign dst_rdy_o = ~last_byte_d1;
+
+ reg [31:0] seq_num;
+ reg [31:0] length;
+
+ wire calc_crc = src_rdy_i & dst_rdy_o;
+
+ crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i),
+ .calc(calc_crc), .crc_out(), .match(match_crc));
+
+ wire first_byte, last_byte;
+ reg second_byte, last_byte_d1;
+
+ assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+ assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+
+ // stubs for now
+ wire match_seq = 1;
+ wire match_len = 1;
+
+ always @(posedge clk)
+ if(reset | clear)
+ last_byte_d1 <= 0;
+ else
+ last_byte_d1 <= last_byte;
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ total <= 0;
+ crc_err <= 0;
+ seq_err <= 0;
+ len_err <= 0;
+ end
+ else
+ if(last_byte_d1)
+ begin
+ total <= total + 1;
+ if(~match_crc)
+ crc_err <= crc_err + 1;
+ else if(~match_seq)
+ seq_err <= seq_err + 1;
+ else if(~match_len)
+ seq_err <= len_err + 1;
+ end
+
+endmodule // packet_verifier
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-02 23:42:12 +0000