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-rw-r--r--usrp2/control_lib/newfifo/fifo19_to_fifo36.v11
1 files changed, 8 insertions, 3 deletions
diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..5f9aeff9b 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
output [35:0] f36_dataout,
output f36_src_rdy_o,
- input f36_dst_rdy_i
+ input f36_dst_rdy_i,
+ output [31:0] debug
);
reg f36_sof, f36_eof, f36_occ;
@@ -50,7 +51,9 @@ module fifo19_to_fifo36
state <= 2;
2 :
if(xfer_out)
- state <= 1;
+ if(~f19_eof)
+ state <= 1;
+ // remain in state 2 if we are at eof
endcase // case(state)
else
if(xfer_out)
@@ -67,5 +70,7 @@ module fifo19_to_fifo36
assign f19_dst_rdy_o = xfer_out | (state != 2);
assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
assign f36_src_rdy_o = (state == 2);
-
+
+ assign debug = state;
+
endmodule // fifo19_to_fifo36