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-rw-r--r--usrp1/common/fpga_regs_common.v117
-rw-r--r--usrp1/common/fpga_regs_standard.v256
-rwxr-xr-xusrp1/inband_lib/rx_buffer_inband.v4
-rw-r--r--usrp1/sdr_lib/adc_interface.v4
-rw-r--r--usrp1/sdr_lib/io_pins.v4
-rw-r--r--usrp1/sdr_lib/master_control_multi.v4
-rw-r--r--usrp1/sdr_lib/rx_buffer.v4
-rw-r--r--usrp1/toplevel/mrfm/mrfm.v4
-rw-r--r--usrp1/toplevel/mrfm/mrfm_proc.v4
-rw-r--r--usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v4
-rw-r--r--usrp1/toplevel/usrp_multi/usrp_multi.v4
-rw-r--r--usrp1/toplevel/usrp_std/usrp_std.v4
12 files changed, 393 insertions, 20 deletions
diff --git a/usrp1/common/fpga_regs_common.v b/usrp1/common/fpga_regs_common.v
new file mode 100644
index 000000000..8035d8565
--- /dev/null
+++ b/usrp1/common/fpga_regs_common.v
@@ -0,0 +1,117 @@
+//
+// This file is machine generated from ./fpga_regs_common.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// This file defines registers common to all FPGA configurations.
+// Registers 0 to 31 are reserved for use in this file.
+
+
+// The FPGA needs to know the rate that samples are coming from and
+// going to the A/D's and D/A's. div = 128e6 / sample_rate
+
+`define FR_TX_SAMPLE_RATE_DIV 7'd0
+`define FR_RX_SAMPLE_RATE_DIV 7'd1
+
+// 2 and 3 are defined in the ATR section
+
+`define FR_MASTER_CTRL 7'd4 // master enable and reset controls
+
+// i/o direction registers for pins that go to daughterboards.
+// Setting the bit makes it an output from the FPGA to the d'board.
+// top 16 is mask, low 16 is value
+
+`define FR_OE_0 7'd5 // slot 0
+`define FR_OE_1 7'd6
+`define FR_OE_2 7'd7
+`define FR_OE_3 7'd8
+
+// i/o registers for pins that go to daughterboards.
+// top 16 is a mask, low 16 is value
+
+`define FR_IO_0 7'd9 // slot 0
+`define FR_IO_1 7'd10
+`define FR_IO_2 7'd11
+`define FR_IO_3 7'd12
+
+`define FR_MODE 7'd13
+
+
+// If the corresponding bit is set, internal FPGA debug circuitry
+// controls the i/o pins for the associated bank of daughterboard
+// i/o pins. Typically used for debugging FPGA designs.
+
+`define FR_DEBUG_EN 7'd14
+
+
+// If the corresponding bit is set, enable the automatic DC
+// offset correction control loop.
+//
+// The 4 low bits are significant:
+//
+// ADC0 = (1 << 0)
+// ADC1 = (1 << 1)
+// ADC2 = (1 << 2)
+// ADC3 = (1 << 3)
+//
+// This control loop works if the attached daugherboard blocks DC.
+// Currently all daughterboards do block DC. This includes:
+// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
+
+`define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable
+
+
+// offset corrections for ADC's and DAC's (2's complement)
+
+`define FR_ADC_OFFSET_0 7'd16
+`define FR_ADC_OFFSET_1 7'd17
+`define FR_ADC_OFFSET_2 7'd18
+`define FR_ADC_OFFSET_3 7'd19
+
+
+// ------------------------------------------------------------------------
+// Automatic Transmit/Receive switching
+//
+// If automatic transmit/receive (ATR) switching is enabled in the
+// FR_ATR_CTL register, the presence or absence of data in the FPGA
+// transmit fifo selects between two sets of values for each of the 4
+// banks of daughterboard i/o pins.
+//
+// Each daughterboard slot has 3 16-bit registers associated with it:
+// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
+//
+// FR_ATR_MASK_{0,1,2,3}:
+//
+// These registers determine which of the daugherboard i/o pins are
+// affected by ATR switching. If a bit in the mask is set, the
+// corresponding i/o bit is controlled by ATR, else it's output
+// value comes from the normal i/o pin output register:
+// FR_IO_{0,1,2,3}.
+//
+// FR_ATR_TXVAL_{0,1,2,3}:
+// FR_ATR_RXVAL_{0,1,2,3}:
+//
+// If the Tx fifo contains data, then the bits from TXVAL that are
+// selected by MASK are output. Otherwise, the bits from RXVAL that
+// are selected by MASK are output.
+
+`define FR_ATR_MASK_0 7'd20 // slot 0
+`define FR_ATR_TXVAL_0 7'd21
+`define FR_ATR_RXVAL_0 7'd22
+
+`define FR_ATR_MASK_1 7'd23 // slot 1
+`define FR_ATR_TXVAL_1 7'd24
+`define FR_ATR_RXVAL_1 7'd25
+
+`define FR_ATR_MASK_2 7'd26 // slot 2
+`define FR_ATR_TXVAL_2 7'd27
+`define FR_ATR_RXVAL_2 7'd28
+
+`define FR_ATR_MASK_3 7'd29 // slot 3
+`define FR_ATR_TXVAL_3 7'd30
+`define FR_ATR_RXVAL_3 7'd31
+
+// Clock ticks to delay rising and falling edge of T/R signal
+`define FR_ATR_TX_DELAY 7'd2
+`define FR_ATR_RX_DELAY 7'd3
+
diff --git a/usrp1/common/fpga_regs_standard.v b/usrp1/common/fpga_regs_standard.v
new file mode 100644
index 000000000..d09aa6116
--- /dev/null
+++ b/usrp1/common/fpga_regs_standard.v
@@ -0,0 +1,256 @@
+//
+// This file is machine generated from ./fpga_regs_standard.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
+// Registers 64 to 79 are available for custom FPGA builds.
+
+
+// DDC / DUC
+
+`define FR_INTERP_RATE 7'd32 // [1,1024]
+`define FR_DECIM_RATE 7'd33 // [1,256]
+
+// DDC center freq
+
+`define FR_RX_FREQ_0 7'd34
+`define FR_RX_FREQ_1 7'd35
+`define FR_RX_FREQ_2 7'd36
+`define FR_RX_FREQ_3 7'd37
+
+// See below for DDC Starting Phase
+
+// ------------------------------------------------------------------------
+// configure FPGA Rx mux
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
+// +-----------------------+-------+-------+-------+-------+-+-----+
+//
+// There are a maximum of 4 digital downconverters in the the FPGA.
+// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
+//
+// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
+//
+// 0 = DDC input is from ADC 0
+// 1 = DDC input is from ADC 1
+// 2 = DDC input is from ADC 2
+// 3 = DDC input is from ADC 3
+//
+// If Z == 1, all DDC Q inputs are set to zero
+// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
+// 8 16-bit values.
+
+`define FR_RX_MUX 7'd38
+
+// ------------------------------------------------------------------------
+// configure FPGA Tx Mux.
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
+// +-----------------------------------------------+-------+-+-----+
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB. The legal values are 1 or 2, corresponding to 2 or 4
+// 16-bit values.
+//
+// There are two interpolators with complex inputs and outputs.
+// There are four DACs. (We use the DUC in each AD9862.)
+//
+// Each 4-bit DACx field specifies the source for the DAC and
+// whether or not that DAC is enabled. Each subfield is coded
+// like this:
+//
+// 3 2 1 0
+// +-+-----+
+// |E| N |
+// +-+-----+
+//
+// Where E is set if the DAC is enabled, and N specifies which
+// interpolator output is connected to this DAC.
+//
+// N which interp output
+// --- -------------------
+// 0 chan 0 I
+// 1 chan 0 Q
+// 2 chan 1 I
+// 3 chan 1 Q
+
+`define FR_TX_MUX 7'd39
+
+// ------------------------------------------------------------------------
+// REFCLK control
+//
+// Control whether a reference clock is sent to the daughterboards,
+// and what frequency. The refclk is sent on d'board i/o pin 0.
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+------------+
+// | Reserved (Must be zero) |E| DIVISOR |
+// +-----------------------------------------------+-+------------+
+
+//
+// Bit 7 -- 1 turns on refclk, 0 allows IO use
+// Bits 6:0 Divider value
+
+`define FR_TX_A_REFCLK 7'd40
+`define FR_RX_A_REFCLK 7'd41
+`define FR_TX_B_REFCLK 7'd42
+`define FR_RX_B_REFCLK 7'd43
+
+
+// ------------------------------------------------------------------------
+// DDC Starting Phase
+
+`define FR_RX_PHASE_0 7'd44
+`define FR_RX_PHASE_1 7'd45
+`define FR_RX_PHASE_2 7'd46
+`define FR_RX_PHASE_3 7'd47
+
+// ------------------------------------------------------------------------
+// Tx data format control register
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-------------------------------------------------------+-------+
+// | Reserved (Must be zero) | FMT |
+// +-------------------------------------------------------+-------+
+//
+// FMT values:
+
+`define FR_TX_FORMAT 7'd48
+
+// ------------------------------------------------------------------------
+// Rx data format control register
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------+-+-+---------+-------+
+// | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
+// +-----------------------------------------+-+-+---------+-------+
+//
+// FMT values:
+
+`define FR_RX_FORMAT 7'd49
+
+
+// The valid combinations currently are:
+//
+// B Q WIDTH SHIFT
+// 0 1 16 0
+// 0 1 8 8
+
+
+// Possible future values of WIDTH = {4, 2, 1}
+// 12 takes a bit more work, since we need to know packet alignment.
+
+// ------------------------------------------------------------------------
+// FIXME register numbers 50 to 63 are available
+
+// ------------------------------------------------------------------------
+// Registers 64 to 95 are reserved for user custom FPGA builds.
+// The standard USRP software will not touch these.
+
+`define FR_USER_0 7'd64
+`define FR_USER_1 7'd65
+`define FR_USER_2 7'd66
+`define FR_USER_3 7'd67
+`define FR_USER_4 7'd68
+`define FR_USER_5 7'd69
+`define FR_USER_6 7'd70
+`define FR_USER_7 7'd71
+`define FR_USER_8 7'd72
+`define FR_USER_9 7'd73
+`define FR_USER_10 7'd74
+`define FR_USER_11 7'd75
+`define FR_USER_12 7'd76
+`define FR_USER_13 7'd77
+`define FR_USER_14 7'd78
+`define FR_USER_15 7'd79
+`define FR_USER_16 7'd80
+`define FR_USER_17 7'd81
+`define FR_USER_18 7'd82
+`define FR_USER_19 7'd83
+`define FR_USER_20 7'd84
+`define FR_USER_21 7'd85
+`define FR_USER_22 7'd86
+`define FR_USER_23 7'd87
+`define FR_USER_24 7'd88
+`define FR_USER_25 7'd89
+`define FR_USER_26 7'd90
+`define FR_USER_27 7'd91
+`define FR_USER_28 7'd92
+`define FR_USER_29 7'd93
+`define FR_USER_30 7'd94
+`define FR_USER_31 7'd95
+
+//Registers needed for multi usrp master/slave configuration
+//
+//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
+//
+`define FR_RX_MASTER_SLAVE 7'd64
+`define bitnoFR_RX_SYNC 0
+`define bitnoFR_RX_SYNC_MASTER 1
+`define bitnoFR_RX_SYNC_SLAVE 2
+
+
+//Caution The master settings will output values on the io lines.
+//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
+//If you set the slave bits then your usrp won't do anything if you don't connect a master.
+// Rx Master/slave control register
+//
+// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
+// This can be done with basic_rx boards or dbsrx boards
+//dbsrx: connect master-J25 to slave-J25
+//basic rx: connect J25 to slave-J25
+//CAUTION: pay attention to the lineup of your connector.
+//The red line (pin1) should be at the same side of the daughterboards on master and slave.
+//If you turnaround the cable on one end you will burn your usrp.
+
+//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
+//You can still link them but you must use only a 2pin or 1pin cable
+//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
+//You can use a cable like the ones found with the leds on the mainbord of a PC.
+//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
+//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
+
+
+// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
+// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
+// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
+`define bitnoFR_RX_SYNC_INPUT_IOPIN 15
+`define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
+//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
+`define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
+`define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
+// =======================================================================
+// READBACK Registers
+// =======================================================================
+
+`define FR_RB_IO_RX_A_IO_TX_A 7'd1 // read back a-side i/o pins
+`define FR_RB_IO_RX_B_IO_TX_B 7'd2 // read back b-side i/o pins
+
+// ------------------------------------------------------------------------
+// FPGA Capability register
+//
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+-----+-+-----+
+// | Reserved (Must be zero) |T|NDUC |R|NDDC |
+// +-----------------------------------------------+-+-----+-+-----+
+//
+// Bottom 4-bits are Rx capabilities
+// Next 4-bits are Tx capabilities
+
+`define FR_RB_CAPS 7'd3
+
+
diff --git a/usrp1/inband_lib/rx_buffer_inband.v b/usrp1/inband_lib/rx_buffer_inband.v
index cbd2d8958..40c7ec7bd 100755
--- a/usrp1/inband_lib/rx_buffer_inband.v
+++ b/usrp1/inband_lib/rx_buffer_inband.v
@@ -1,5 +1,5 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
+//`include "../common/fpga_regs_common.v"
+//`include "../common/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
diff --git a/usrp1/sdr_lib/adc_interface.v b/usrp1/sdr_lib/adc_interface.v
index f18ffc104..cb78f332a 100644
--- a/usrp1/sdr_lib/adc_interface.v
+++ b/usrp1/sdr_lib/adc_interface.v
@@ -1,7 +1,7 @@
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
module adc_interface
(input clock, input reset, input enable,
diff --git a/usrp1/sdr_lib/io_pins.v b/usrp1/sdr_lib/io_pins.v
index ad1b7b4a8..b8bf59555 100644
--- a/usrp1/sdr_lib/io_pins.v
+++ b/usrp1/sdr_lib/io_pins.v
@@ -19,8 +19,8 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
diff --git a/usrp1/sdr_lib/master_control_multi.v b/usrp1/sdr_lib/master_control_multi.v
index cab96a79f..eee8ebfa3 100644
--- a/usrp1/sdr_lib/master_control_multi.v
+++ b/usrp1/sdr_lib/master_control_multi.v
@@ -19,8 +19,8 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
// Clock, enable, and reset controls for whole system
// Modified version to enable multi_usrp synchronisation
diff --git a/usrp1/sdr_lib/rx_buffer.v b/usrp1/sdr_lib/rx_buffer.v
index d17294b98..5541d2912 100644
--- a/usrp1/sdr_lib/rx_buffer.v
+++ b/usrp1/sdr_lib/rx_buffer.v
@@ -22,8 +22,8 @@
// Interface to Cypress FX2 bus
// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
module rx_buffer
( // Read/USB side
diff --git a/usrp1/toplevel/mrfm/mrfm.v b/usrp1/toplevel/mrfm/mrfm.v
index 7a0e38059..6b7442ef3 100644
--- a/usrp1/toplevel/mrfm/mrfm.v
+++ b/usrp1/toplevel/mrfm/mrfm.v
@@ -24,8 +24,8 @@
// Uncomment the following to include optional circuitry
`include "mrfm.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
module mrfm
(output MYSTERY_SIGNAL,
diff --git a/usrp1/toplevel/mrfm/mrfm_proc.v b/usrp1/toplevel/mrfm/mrfm_proc.v
index 80de9fc90..7da934a6e 100644
--- a/usrp1/toplevel/mrfm/mrfm_proc.v
+++ b/usrp1/toplevel/mrfm/mrfm_proc.v
@@ -1,7 +1,7 @@
`include "mrfm.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
module mrfm_proc (input clock, input reset, input enable,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
index 79f0dfa4a..49ed7444d 100644
--- a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
+++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
@@ -23,8 +23,8 @@
`define RX_IN_BAND
`include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.v b/usrp1/toplevel/usrp_multi/usrp_multi.v
index ce484fc1c..08ae0c2aa 100644
--- a/usrp1/toplevel/usrp_multi/usrp_multi.v
+++ b/usrp1/toplevel/usrp_multi/usrp_multi.v
@@ -29,8 +29,8 @@
// Uncomment the following to include optional circuitry
`include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
module usrp_multi
(output MYSTERY_SIGNAL,
diff --git a/usrp1/toplevel/usrp_std/usrp_std.v b/usrp1/toplevel/usrp_std/usrp_std.v
index 8b29a9c21..b2eaceb25 100644
--- a/usrp1/toplevel/usrp_std/usrp_std.v
+++ b/usrp1/toplevel/usrp_std/usrp_std.v
@@ -28,8 +28,8 @@
// Uncomment the following to include optional circuitry
`include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
module usrp_std
(output MYSTERY_SIGNAL,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 20:12:11 +0000