diff options
Diffstat (limited to 'toplevel/usrp_inband_usb/usrp_inband_usb.qsf')
| -rw-r--r-- | toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 2646d831f..8296a453e 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1" # Pin & Location Assignments # ========================== @@ -371,6 +371,13 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v @@ -405,5 +412,4 @@ set_global_assignment -name VERILOG_FILE usrp_inband_usb.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
\ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file |