diff options
Diffstat (limited to 'top')
| -rw-r--r-- | top/u2_core/u2_core.v | 17 | ||||
| -rw-r--r-- | top/u2_rev3/Makefile | 13 |
2 files changed, 26 insertions, 4 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index f9ac07a55..ada0f66db 100644 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -419,19 +419,30 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); + + udp_wrapper #(.BASE(0)) udp_wrapper + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), + .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), .rx_f36_dst_rdy_i(wr2_ready_o), + .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), .tx_f36_dst_rdy_o(rd2_ready_i) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile index 1f8bbe304..d27469f47 100644 --- a/top/u2_rev3/Makefile +++ b/top/u2_rev3/Makefile @@ -88,7 +88,12 @@ vrt/vita_rx_control.v \ vrt/vita_rx_framer.v \ vrt/vita_tx_control.v \ vrt/vita_tx_deframer.v \ +udp/udp_wrapper.v \ +udp/fifo19_rxrealign.v \ +udp/prot_eng_tx.v \ +udp/add_onescomp.v \ simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac_wrapper19.v \ simple_gemac/simple_gemac.v \ simple_gemac/simple_gemac_wb.v \ simple_gemac/simple_gemac_tx.v \ @@ -109,11 +114,15 @@ control_lib/newfifo/buffer_pool.v \ control_lib/newfifo/fifo_2clock.v \ control_lib/newfifo/fifo_2clock_cascade.v \ control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo19_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo19.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -123,6 +132,8 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x19_2clk.v \ +coregen/fifo_xlnx_16x19_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ |