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-rw-r--r--top/eth_test/eth_sim_top.v437
-rw-r--r--top/eth_test/eth_tb.v257
-rw-r--r--top/single_u2_sim/single_u2_sim.v322
-rw-r--r--top/tcl/ise_helper.tcl89
-rwxr-xr-xtop/u2_core/u2_core.v678
-rw-r--r--top/u2_fpga/Makefile129
-rw-r--r--top/u2_fpga/u2_fpga.isebin0 -> 477678 bytes
-rwxr-xr-xtop/u2_fpga/u2_fpga.ucf341
-rw-r--r--top/u2_fpga/u2_fpga_top.prj102
-rw-r--r--top/u2_fpga/u2_fpga_top.v393
-rw-r--r--top/u2_rev2/Makefile257
-rw-r--r--top/u2_rev2/u2_rev2.ucf337
-rw-r--r--top/u2_rev2/u2_rev2.v413
-rw-r--r--top/u2_rev3/Makefile244
-rw-r--r--top/u2_rev3/u2_rev3.ucf333
-rw-r--r--top/u2_rev3/u2_rev3.v426
-rwxr-xr-xtop/u2plus/u2plus.ucf280
-rw-r--r--top/u2plus/u2plus.v377
18 files changed, 5415 insertions, 0 deletions
diff --git a/top/eth_test/eth_sim_top.v b/top/eth_test/eth_sim_top.v
new file mode 100644
index 000000000..640a4e60f
--- /dev/null
+++ b/top/eth_test/eth_sim_top.v
@@ -0,0 +1,437 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: u2_basic
+//////////////////////////////////////////////////////////////////////////////////
+
+module eth_sim_top
+ (// Clocks
+ input dsp_clk,
+ input wb_clk,
+ output clock_ready,
+ input clk_to_mac,
+ input pps_in,
+
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in,
+ output exp_pps_out,
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output [7:0] GMII_TXD,
+ output GMII_TX_EN,
+ output GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ input PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output [15:0] ser_t,
+ output ser_tklsb,
+ output ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start,
+ output cpld_mode,
+ output cpld_done,
+ input cpld_din,
+ input cpld_clk,
+ input cpld_detached,
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+ // I2C
+ input scl_pad_i,
+ output scl_pad_o,
+ output scl_pad_oen_o,
+ input sda_pad_i,
+ output sda_pad_o,
+ output sda_pad_oen_o,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Generic SPI
+ output sclk,
+ output mosi,
+ input miso,
+ output sen_clk,
+ output sen_dac,
+ output sen_tx_db,
+ output sen_tx_adc,
+ output sen_tx_dac,
+ output sen_rx_db,
+ output sen_rx_adc,
+ output sen_rx_dac,
+
+ // GPIO to DBoards
+ inout [15:0] io_tx,
+ inout [15:0] io_rx
+ );
+
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+ wire set_stb;
+
+ wire ram_loader_done;
+ wire ram_loader_rst, wb_rst, dsp_rst;
+
+ wire [31:0] ser_debug;
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////
+ // Wishbone Single Master INTERCON
+ parameter dw = 32; // Data bus width
+ parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space
+ parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity.
+
+ wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+ wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+ s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i;
+ wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+ wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel;
+ wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack;
+ wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb;
+ wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc;
+ wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err;
+ wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty;
+ wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we;
+
+ wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
+ .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010),
+ .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101),
+ .dw(dw),.aw(aw),.sw(sw)) wb_1master
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+
+ .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+ .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+ .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+ .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+ .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+ .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+ .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+ .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+ .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+ .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+ .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+ .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+ .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+ .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+ .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+ .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+ .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+ .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
+ );
+
+ //////////////////////////////////////////////////////////////////////////////////////////
+ // Reset Controller
+ system_control sysctrl (.wb_clk_i(wb_clk),
+ .ram_loader_rst_o(ram_loader_rst),
+ .wb_rst_o(wb_rst),
+ .ram_loader_done_i(ram_loader_done));
+
+ // ///////////////////////////////////////////////////////////////////
+ // RAM Loader
+ wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we;
+ wire [3:0] iram_wr_sel;
+ wire [aw-1:0] iram_wr_adr, iram_rd_adr;
+ wire [dw-1:0] iram_wr_dat, iram_rd_dat;
+
+ wire bus_error, proc_int;
+
+ assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
+ assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
+
+ ram_loader #(.AWIDTH(16))
+ ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ // CPLD Interface
+ .cfg_clk_i(cpld_clk),
+ .cfg_data_i(cpld_din),
+ .start_o(cpld_start),
+ .mode_o(cpld_mode),
+ .done_o(cpld_done),
+ .detached_i(cpld_detached),
+ // Wishbone Interface
+ .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr),
+ .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel),
+ .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack),
+ .ram_loader_done_o(ram_loader_done));
+
+ // Processor
+ aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
+ aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+ // Instruction Wishbone bus to I-RAM
+ .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr),
+ .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack),
+ // Data Wishbone bus to system bus fabric
+ .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+ .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+ // Interrupts and exceptions
+ .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+ assign bus_error = m0_err | m0_rty;
+ assign proc_int = 1'b0;
+
+ // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+ // I-port connects directly to processor and ram loader
+
+ ram_wb_harvard #(.AWIDTH(14))
+ ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+
+ .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat),
+ .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb),
+ .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
+
+ .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
+ .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
+
+ assign s0_err = 1'b0;
+ assign s0_rty = 1'b0;
+
+ // Buffer Pool, slave #1
+ wire rd0_read, rd0_ready, rd0_done, rd0_empty;
+ wire rd1_read, rd1_ready, rd1_done, rd1_empty;
+ wire rd2_read, rd2_ready, rd2_done, rd2_empty;
+ wire rd3_read, rd3_ready, rd3_done, rd3_empty;
+ wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+ wire wr0_write, wr0_done, wr0_ready, wr0_full;
+ wire wr1_write, wr1_done, wr1_ready, wr1_full;
+ wire wr2_write, wr2_done, wr2_ready, wr2_full;
+ wire wr3_write, wr3_done, wr3_ready, wr3_full;
+ wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+/*
+ buffer_pool buffer_pool
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+ .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+
+ .stream_clk(dsp_clk),.stream_rst(dsp_rst),
+ // Write Interfaces
+ .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(),
+ .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(),
+ .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(),
+ .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(),
+ // Read Interfaces
+ .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty),
+ .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty),
+ .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty),
+ .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty)
+ );
+*/
+ // SPI -- Slave #2
+ spi_top shared_spi
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+ .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
+
+ .wb_err_o(s2_err),.wb_int_o(s2_int),
+ .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+ assign s2_rty = 1'b0;
+
+ // I2C -- Slave #3
+ i2c_master_top #(.ARST_LVL(1))
+ i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
+ .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i),
+ .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+ .wb_ack_o(s3_ack),.wb_inta_o(st_int),
+ .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+ .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+ assign s3_err = 1'b0;
+ assign s3_rty = 1'b0;
+
+ // GPIOs -- Slave #4
+ wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d;
+ assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d;
+
+ simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we),
+ .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a),
+ .gpio(/* io_tx[7:0]*/) );
+
+ simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we),
+ .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b),
+ .gpio(/* io_tx[15:8] */) );
+
+ simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we),
+ .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c),
+ .gpio(/* io_rx[7:0] */) );
+
+ simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we),
+ .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d),
+ .gpio(/* io_rx[15:8]*/) );
+
+ assign s4_err = 1'b0;
+ assign s4_rty = 1'b0;
+
+ // Output control lines, SLAVE #5
+ wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs;
+ assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+ assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+ assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+ assign {led2, led1} = misc_outs[1:0];
+
+ wb_output_pins32 control_lines
+ (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i),
+ .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc),
+ .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) );
+
+ assign s5_err = 1'b0;
+ assign s5_rty = 1'b0;
+
+ // Ethernet slave, #6
+ eth_wrapper eth_wrapper
+ (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(),
+ .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode
+ .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER),
+ .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL),
+ .Mdio(MDIO),.Mdc(MDC),
+ // FIFO Interfaces
+ .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(),
+ .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(),
+ // Wishbone
+ .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack)
+ );
+
+ assign s6_err = 1'b0;
+ assign s6_rty = 1'b0;
+
+ // Settings Bus -- Slave #7
+ settings_bus settings_bus
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+ .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+ .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+
+ assign s7_err = 1'b0;
+ assign s7_rty = 1'b0;
+ assign s7_dat_i = 32'd0;
+
+ ///////////////////////////////////////////////////////////////////////////
+ // DSP
+ reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+ reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg1 <= adc_a;
+ adc_a_reg2 <= adc_a_reg1;
+ adc_b_reg1 <= adc_b;
+ adc_b_reg2 <= adc_b_reg1;
+ adc_ovf_a_reg1 <= adc_ovf_a;
+ adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+ adc_ovf_b_reg1 <= adc_ovf_b;
+ adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+ end // always @ (posedge dsp_clk)
+
+ dsp_core_rx dsp_core_rx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+ .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),
+ .rx_ready_i(wr1_ready),.rx_full_i(wr1_full),
+ .overrun() );
+
+ dsp_core_tx dsp_core_tx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),
+ .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty),
+ .underrun() );
+
+ assign dsp_rst = wb_rst;
+
+ /////////////////////////////////////////////////////////////////////////////////////
+ // SERDES
+ serdes_tx serdes_tx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+ .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),
+ .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
+ );
+
+ serdes_rx serdes_rx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+ .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done)
+ );
+
+ // Debug Pins
+ wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+ {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+ {8'hAF},
+ {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+
+ wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
+ {iram_rd_adr[15:8]},
+ {iram_rd_adr[7:0]},
+ {serdes_outs}};
+
+ assign io_rx = ser_debug[31:16];
+ assign io_tx = ser_debug[15:0];
+
+ assign debug = debug_wb;
+
+ assign debug_clk[0] = wb_clk;
+ assign debug_clk[1] = dsp_clk;
+
+endmodule // eth_test
+
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/top/eth_test/eth_tb.v b/top/eth_test/eth_tb.v
new file mode 100644
index 000000000..451ce1e7e
--- /dev/null
+++ b/top/eth_test/eth_tb.v
@@ -0,0 +1,257 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module eth_tb();
+ // Misc, debug
+ wire led1;
+ wire led2;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ // Expansion
+ wire exp_pps_in;
+ wire exp_pps_out;
+
+ // GMII
+ // GMII-CTRL
+ wire GMII_COL;
+ wire GMII_CRS;
+
+ // GMII-TX
+ wire [7:0] GMII_TXD;
+ wire GMII_TX_EN;
+ wire GMII_TX_ER;
+ wire GMII_GTX_CLK;
+ wire GMII_TX_CLK; // 100mbps clk
+
+ // GMII-RX
+ wire [7:0] GMII_RXD;
+ wire GMII_RX_CLK;
+ wire GMII_RX_DV;
+ wire GMII_RX_ER;
+
+ // GMII-Management
+ wire MDIO;
+ wire MDC;
+ wire PHY_INTn; // open drain
+ wire PHY_RESETn;
+ wire PHY_CLK; // possibly use on-board osc
+
+ // RAM
+ wire [17:0] RAM_D;
+ wire [18:0] RAM_A;
+ wire RAM_CE1n;
+ wire RAM_CENn;
+ wire RAM_CLK;
+ wire RAM_WEn;
+ wire RAM_OEn;
+ wire RAM_LDn;
+
+ // SERDES
+ wire ser_enable;
+ wire ser_prbsen;
+ wire ser_loopen;
+ wire ser_rx_en;
+
+ wire ser_tx_clk;
+ wire [15:0] ser_t;
+ wire ser_tklsb;
+ wire ser_tkmsb;
+
+ wire ser_rx_clk;
+ wire [15:0] ser_r;
+ wire ser_rklsb;
+ wire ser_rkmsb;
+
+ // CPLD interface
+ wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+
+ // ADC
+ wire [13:0] adc_a;
+ wire adc_ovf_a;
+ wire adc_oen_a;
+ wire adc_pdn_a;
+
+ wire [13:0] adc_b;
+ wire adc_ovf_b;
+ wire adc_oen_b;
+ wire adc_pdn_b;
+
+ // DAC
+ wire [15:0] dac_a;
+ wire [15:0] dac_b;
+
+ // I2C
+ wire SCL;
+ wire SDA;
+
+ // Clock Gen Control
+ wire [1:0] clk_en;
+ wire [1:0] clk_sel;
+ wire clk_func; // FIXME is an input to control the 9510
+ wire clk_status;
+
+ // Clocks
+ reg clk_fpga;
+ wire clk_to_mac;
+ wire pps_in;
+
+ // Generic SPI
+ wire sclk, mosi, miso;
+ wire sen_clk;
+ wire sen_dac;
+ wire sen_tx_db;
+ wire sen_tx_adc;
+ wire sen_tx_dac;
+ wire sen_rx_db;
+ wire sen_rx_adc;
+ wire sen_rx_dac;
+
+ // GPIO to DBoards
+ wire [15:0] io_tx;
+ wire [15:0] io_rx;
+
+ wire wb_clk, wb_rst;
+ wire start, clock_ready;
+
+ reg aux_clk;
+
+ initial aux_clk= 1'b0;
+ always #25 aux_clk = ~aux_clk;
+
+ initial clk_fpga = 1'bx;
+ initial #3007 clk_fpga = 1'b0;
+ always #7 clk_fpga = ~clk_fpga;
+
+
+ wire div_clk;
+ reg [2:0] div_ctr = 0;
+
+ always @(posedge clk_fpga or negedge clk_fpga)
+ if(div_ctr==5)
+ div_ctr = 0;
+ else
+ div_ctr = div_ctr + 1;
+ assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
+
+ assign dsp_clk = clk_fpga;
+ assign wb_clk = clock_ready ? div_clk : aux_clk;
+
+ initial
+ $monitor($time, ,clock_ready);
+
+ initial begin
+ $dumpfile("eth_tb.vcd");
+ $dumpvars(0,eth_tb);
+ end
+
+ initial #10000000 $finish;
+
+ cpld_model
+ cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+ .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+
+ eth_sim_top eth_sim_top(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .led1 (led1),
+ .led2 (led2),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]));
+
+ // Experimental printf-like function
+ always @(posedge wb_clk)
+ begin
+ if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000))
+ $write("%x",eth_sim_top.m0_dat_i);
+ if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100))
+ $display("%x",eth_sim_top.m0_dat_i);
+ if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004))
+ $write("%c",eth_sim_top.m0_dat_i);
+ if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104))
+ $display("%c",eth_sim_top.m0_dat_i);
+ if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008))
+ $display("");
+ end
+
+
+endmodule // u2_sim_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/top/single_u2_sim/single_u2_sim.v b/top/single_u2_sim/single_u2_sim.v
new file mode 100644
index 000000000..4e891d384
--- /dev/null
+++ b/top/single_u2_sim/single_u2_sim.v
@@ -0,0 +1,322 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module single_u2_sim();
+ // Misc, debug
+ wire [7:0] leds;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ // Expansion
+ wire exp_pps_in;
+ wire exp_pps_out;
+
+ // GMII
+ // GMII-CTRL
+ wire GMII_COL;
+ wire GMII_CRS;
+
+ // GMII-TX
+ wire [7:0] GMII_TXD;
+ wire GMII_TX_EN;
+ wire GMII_TX_ER;
+ wire GMII_GTX_CLK;
+ wire GMII_TX_CLK; // 100mbps clk
+
+ // GMII-RX
+ wire [7:0] GMII_RXD;
+ wire GMII_RX_CLK;
+ wire GMII_RX_DV;
+ wire GMII_RX_ER;
+
+ // GMII-Management
+ wire MDIO;
+ wire MDC;
+ wire PHY_INTn; // open drain
+ wire PHY_RESETn;
+ wire PHY_CLK; // possibly use on-board osc
+
+ // RAM
+ wire [17:0] RAM_D;
+ wire [18:0] RAM_A;
+ wire RAM_CE1n;
+ wire RAM_CENn;
+ wire RAM_CLK;
+ wire RAM_WEn;
+ wire RAM_OEn;
+ wire RAM_LDn;
+
+ // SERDES
+ wire ser_enable;
+ wire ser_prbsen;
+ wire ser_loopen;
+ wire ser_rx_en;
+
+ wire ser_tx_clk;
+ wire [15:0] ser_t;
+ wire ser_tklsb;
+ wire ser_tkmsb;
+
+ wire ser_rx_clk;
+ wire [15:0] ser_r;
+ wire ser_rklsb;
+ wire ser_rkmsb;
+
+ // CPLD interface
+ wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+
+ // ADC
+ wire [13:0] adc_a;
+ wire adc_ovf_a;
+ wire adc_on_a, adc_oe_a;
+
+ wire [13:0] adc_b;
+ wire adc_ovf_b;
+ wire adc_on_b, adc_oe_b;
+
+ // DAC
+ wire [15:0] dac_a;
+ wire [15:0] dac_b;
+
+ // I2C
+ wire SCL;
+ wire SDA;
+
+ // Clock Gen Control
+ wire [1:0] clk_en;
+ wire [1:0] clk_sel;
+ wire clk_func; // FIXME is an input to control the 9510
+ wire clk_status;
+
+ // Clocks
+ reg clk_fpga;
+ reg clk_to_mac;
+ wire pps_in;
+
+ // Generic SPI
+ wire sclk, mosi, miso;
+ wire sen_clk;
+ wire sen_dac;
+ wire sen_tx_db;
+ wire sen_tx_adc;
+ wire sen_tx_dac;
+ wire sen_rx_db;
+ wire sen_rx_adc;
+ wire sen_rx_dac;
+
+ // GPIO to DBoards
+ wire [15:0] io_tx;
+ wire [15:0] io_rx;
+
+ wire wb_clk;
+ wire start, clock_ready;
+
+ reg aux_clk;
+
+ initial aux_clk= 1'b0;
+ always #6 aux_clk = ~aux_clk;
+
+ initial clk_fpga = 1'bx;
+ initial #3007 clk_fpga = 1'b0;
+ always #5 clk_fpga = ~clk_fpga;
+
+ initial clk_to_mac = 0;
+ always #4 clk_to_mac = ~clk_to_mac;
+
+ wire div_clk, dsp_clk;
+ reg [7:0] div_ctr = 0;
+
+ assign dsp_clk = clock_ready ? clk_fpga : aux_clk;
+ assign wb_clk = div_clk;
+
+`define CLK_DIV_2 1
+//`define CLK_DIV_3
+
+`ifdef CLK_DIV_2
+ localparam clock_divider = 4'd2;
+ always @(posedge dsp_clk)
+ div_ctr <= div_ctr + 1;
+ assign div_clk = div_ctr[0];
+`endif
+
+`ifdef CLK_DIV_3
+ localparam clock_divider = 2;
+ always @(posedge dsp_clk or negedge dsp_clk)
+ if(div_ctr == 5)
+ div_ctr <= 0;
+ else
+ div_ctr <= div_ctr + 1;
+ assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2));
+`endif
+
+ initial
+ $monitor($time, ,clock_ready);
+
+ always #1000000 $monitor("Time in ns ",$time);
+
+ initial begin
+ @(negedge cpld_done);
+ @(posedge cpld_done);
+ $dumpfile("single_u2_sim.lxt");
+ $dumpvars(0,single_u2_sim);
+ end
+
+ initial #10000000 $finish;
+
+ cpld_model
+ cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+ .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+
+ serdes_model serdes_model
+ (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
+ .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
+ .even(0),.error(0) );
+
+ adc_model adc_model
+ (.clk(dsp_clk),.rst(0),
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a),
+ .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) );
+
+ wire [2:0] speed;
+ Phy_sim phy_model
+ (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK),
+ .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD),
+ .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD),
+ .Crs(GMII_CRS), .Col(GMII_COL),
+ .Speed(speed), .Done(0) );
+ pullup p3(MDIO);
+
+ miim_model miim_model
+ (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK),
+ .phy_intn_o(PHY_INTn),.speed_o(speed) );
+
+ xlnx_glbl glbl (.GSR(),.GTS());
+
+ wire RAM_MODE = 1'b0;
+ cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
+ .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
+ .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
+ .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) );
+
+ M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0),
+ .SDA(SDA),.SCL(SCL),.RESET(0));
+
+ wire scl_pad_i, scl_pad_o, scl_pad_oen_o;
+ wire sda_pad_i, sda_pad_o, sda_pad_oen_o;
+
+ pullup p1(SCL);
+ pullup p2(SDA);
+
+ assign scl_pad_i = SCL;
+ assign sda_pad_i = SDA;
+
+ assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o;
+ assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o;
+
+ // printf output
+ wire uart_baud_o, uart_tx_o, uart_rx_i;
+ assign uart_rx_i = 1'b1;
+
+ uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
+
+ // End the simulation
+ always @(posedge wb_clk)
+ if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0))
+ begin
+ $display($time, "Finish called.",);
+ $finish;
+ end
+
+ u2_core #(.RAM_SIZE(24576))
+ u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ .uart_rx_i (uart_rx_i),
+ .uart_baud_o (uart_baud_o),
+ .sim_mode (1'b1),
+ .clock_divider (clock_divider)
+ );
+
+endmodule // single_u2_sim
diff --git a/top/tcl/ise_helper.tcl b/top/tcl/ise_helper.tcl
new file mode 100644
index 000000000..fe9db87af
--- /dev/null
+++ b/top/tcl/ise_helper.tcl
@@ -0,0 +1,89 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+proc set_props {process options} {
+ if ![string compare $options ""] {
+ return
+ }
+ set state 1
+ foreach opt $options {
+ if $state {
+ set key $opt
+ set state 0
+ } else {
+ puts ">>> Setting: $process\[$key\] = $opt"
+ if ![string compare $process "Project"] {
+ project set $key $opt
+ } else {
+ project set $key $opt -process $process
+ }
+ set state 1
+ }
+ }
+}
+
+if [file isfile $env(PROJ_FILE)] {
+ puts ">>> Opening project: $env(PROJ_FILE)"
+ project open $env(PROJ_FILE)
+} else {
+ puts ">>> Creating project: $env(PROJ_FILE)"
+ project new $env(PROJ_FILE)
+
+ ##################################################
+ # Set the project properties
+ ##################################################
+ set_props "Project" $env(PROJECT_PROPERTIES)
+
+ ##################################################
+ # Add the sources
+ ##################################################
+ foreach source $env(SOURCES) {
+ set source $env(SOURCE_ROOT)$source
+ puts ">>> Adding source to project: $source"
+ xfile add $source
+ }
+
+ ##################################################
+ # Set the top level module
+ ##################################################
+ project set top $env(TOP_MODULE)
+
+ ##################################################
+ # Set the process properties
+ ##################################################
+ set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES)
+ set_props "Translate" $env(TRANSLATE_PROPERTIES)
+ set_props "Map" $env(MAP_PROPERTIES)
+ set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES)
+ set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES)
+ set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES)
+ set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
+}
+
+if [string compare $env(PROCESS_RUN) ""] {
+ puts ">>> Running Process: $env(PROCESS_RUN)"
+ process run $env(PROCESS_RUN)
+}
+
+project close
+exit
+
+
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
new file mode 100755
index 000000000..cc5a35c76
--- /dev/null
+++ b/top/u2_core/u2_core.v
@@ -0,0 +1,678 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name: u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+ #(parameter RAM_SIZE=16384)
+ (// Clocks
+ input dsp_clk,
+ input wb_clk,
+ output clock_ready,
+ input clk_to_mac,
+ input pps_in,
+
+ // Misc, debug
+ output [7:0] leds,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in,
+ output exp_pps_out,
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output [7:0] GMII_TXD,
+ output GMII_TX_EN,
+ output GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output [15:0] ser_t,
+ output ser_tklsb,
+ output ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start,
+ output cpld_mode,
+ output cpld_done,
+ input cpld_din,
+ input cpld_clk,
+ input cpld_detached,
+ //input por,
+ //output config_success,
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_on_a,
+ output adc_oe_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_on_b,
+ output adc_oe_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+ // I2C
+ input scl_pad_i,
+ output scl_pad_o,
+ output scl_pad_oen_o,
+ input sda_pad_i,
+ output sda_pad_o,
+ output sda_pad_oen_o,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Generic SPI
+ output sclk,
+ output mosi,
+ input miso,
+ output sen_clk,
+ output sen_dac,
+ output sen_tx_db,
+ output sen_tx_adc,
+ output sen_tx_dac,
+ output sen_rx_db,
+ output sen_rx_adc,
+ output sen_rx_dac,
+
+ // GPIO to DBoards
+ inout [15:0] io_tx,
+ inout [15:0] io_rx,
+
+ // External RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ input RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // Debug stuff
+ output uart_tx_o,
+ input uart_rx_i,
+ output uart_baud_o,
+ input sim_mode,
+ input [3:0] clock_divider
+ );
+
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+ wire set_stb;
+
+ wire ram_loader_done;
+ wire ram_loader_rst, wb_rst, dsp_rst;
+
+ wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+ wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+
+ wire [31:0] debug_gpio_0, debug_gpio_1;
+ wire [31:0] atr_lines;
+
+ wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+ debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+
+ wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+ wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+ wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+
+ // ///////////////////////////////////////////////////////////////////////////////////////////////
+ // Wishbone Single Master INTERCON
+ parameter dw = 32; // Data bus width
+ parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space
+ parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity.
+
+ wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+ wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+ s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+ s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
+ s12_dat_i, s12_dat_o;
+ wire [aw-1:0] m0_adr,m1_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr;
+ wire [sw-1:0] m0_sel,m1_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel;
+ wire m0_ack,m1_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack;
+ wire m0_stb,m1_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb;
+ wire m0_cyc,m1_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc;
+ wire m0_err,m1_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err;
+ wire m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty;
+ wire m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we;
+
+ wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
+ .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
+ .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
+ .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
+ .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
+ .dw(dw),.aw(aw),.sw(sw)) wb_1master
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+ .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+ .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+ .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+ .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+ .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+ .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+ .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+ .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+ .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+ .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+ .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+ .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+ .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+ .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+ .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+ .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+ .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+ .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+ .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+ .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+ .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
+ .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
+ .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
+ .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
+ .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
+ .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
+ .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
+ .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0),
+ .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
+ .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) );
+
+ //////////////////////////////////////////////////////////////////////////////////////////
+ // Reset Controller
+ system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+ .ram_loader_rst_o(ram_loader_rst),
+ .wb_rst_o(wb_rst),
+ .ram_loader_done_i(ram_loader_done));
+
+ //assign config_success = ram_loader_done;
+
+ // ///////////////////////////////////////////////////////////////////
+ // RAM Loader
+
+ wire [31:0] ram_loader_dat, iwb_dat;
+ wire [15:0] ram_loader_adr, iwb_adr;
+ wire [3:0] ram_loader_sel;
+ wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire iwb_ack, iwb_stb;
+ ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+ ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ // CPLD Interface
+ .cfg_clk_i(cpld_clk),
+ .cfg_data_i(cpld_din),
+ .start_o(cpld_start),
+ .mode_o(cpld_mode),
+ .done_o(cpld_done),
+ .detached_i(cpld_detached),
+ // Wishbone Interface
+ .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+ .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+ .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+ .ram_loader_done_o(ram_loader_done));
+
+ // Processor
+ aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+ aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+ // Instruction Wishbone bus to I-RAM
+ .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+ .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ // Data Wishbone bus to system bus fabric
+ .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+ .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+ // Interrupts and exceptions
+ .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+ assign bus_error = m0_err | m0_rty;
+
+ // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+ // I-port connects directly to processor and ram loader
+
+ ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+
+ .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+ .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+ .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_done_i(ram_loader_done),
+
+ .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+ .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+
+ .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+ .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+
+ assign s0_err = 1'b0;
+ assign s0_rty = 1'b0;
+
+ // Buffer Pool, slave #1
+ wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
+ wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
+ wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
+ wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
+ wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+ wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
+ wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
+ wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
+ wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
+ wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+ buffer_pool buffer_pool
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+ .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+
+ .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .status(status),.sys_int_o(buffer_int),
+
+ .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+ .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+
+ // Write Interfaces
+ .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
+ .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
+ .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
+ .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
+ .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
+ .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
+ .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
+ .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
+ // Read Interfaces
+ .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
+ .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
+ .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
+ .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
+ .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
+ .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
+ .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
+ .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
+ );
+
+ // SPI -- Slave #2
+ spi_top shared_spi
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+ .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+ .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
+ .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+ assign s2_rty = 1'b0;
+
+ // I2C -- Slave #3
+ i2c_master_top #(.ARST_LVL(1))
+ i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
+ .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+ .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+ .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+ .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+ .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+ assign s3_dat_i[31:8] = 24'd0;
+ assign s3_err = 1'b0;
+ assign s3_rty = 1'b0;
+
+ // GPIOs -- Slave #4
+ nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+ .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+ .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+ .gpio( {io_tx,io_rx} ) );
+ assign s4_err = 1'b0;
+ assign s4_rty = 1'b0;
+
+ // Buffer Pool Status -- Slave #5
+ wb_readback_mux buff_pool_status
+ (.wb_clk_i(wb_clk),
+ .wb_rst_i(wb_rst),
+ .wb_stb_i(s5_stb),
+ .wb_adr_i(s5_adr),
+ .wb_dat_o(s5_dat_i),
+ .wb_ack_o(s5_ack),
+
+ .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+ .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+ .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}),
+ .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
+ );
+
+ assign s5_err = 1'b0;
+ assign s5_rty = 1'b0;
+
+ // Slave, #6 Ethernet MAC, see below
+
+ // Settings Bus -- Slave #7
+ settings_bus settings_bus
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+ .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+ .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+
+ assign s7_err = 1'b0;
+ assign s7_rty = 1'b0;
+ assign s7_dat_i = 32'd0;
+
+ // Output control lines
+ wire [7:0] clock_outs, serdes_outs, adc_outs;
+ assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+ assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+ assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+ wire phy_reset;
+ assign PHY_RESETn = ~phy_reset;
+
+ setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+ .in(set_data),.out(clock_outs),.changed());
+ setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(serdes_outs),.changed());
+ setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(adc_outs),.changed());
+ setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(leds),.changed());
+ setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(phy_reset),.changed());
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Ethernet MAC Slave #6
+
+ wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
+ wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
+ wire [31:0] Tx_mac_data, Rx_mac_data;
+ wire [1:0] Tx_mac_BE, Rx_mac_BE;
+ wire rst_mac;
+
+ oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac));
+
+ MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
+ MAC_top
+ (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),
+ .rst_mac(rst_mac),.rst_user(dsp_rst),
+ .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
+ .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
+ .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
+ .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+ .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+ .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+ .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
+ .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
+ .Crs(GMII_CRS),.Col(GMII_COL),
+ .Mdio(MDIO),.Mdc(MDC),
+ .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
+ .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
+ .debug0(debug_mac0),.debug1(debug_mac1) );
+
+ assign s6_err = 1'b0;
+ assign s6_rty = 1'b0;
+
+ mac_rxfifo_int mac_rxfifo_int
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+ .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
+ .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+ .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
+ .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
+ .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
+
+ mac_txfifo_int mac_txfifo_int
+ (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
+ .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+ .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+ .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
+ .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
+ .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Interrupt Controller, Slave #8
+
+ wire [8:0] irq={{6'b0,uart_tx_int, uart_rx_int},
+ {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+
+ simple_pic #(.is(9),.dwidth(32)) simple_pic
+ (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
+ .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+ .irq(irq) );
+ assign s8_err = 0;
+ assign s8_rty = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Master Timer, Slave #9
+
+ wire [31:0] master_time;
+ timer timer
+ (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
+ .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+ .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
+ assign s9_err = 0;
+ assign s9_rty = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // UART, Slave #10
+
+ simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
+ .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+ .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+ .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+
+ assign s10_err = 0;
+ assign s10_rty = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // ATR Controller, Slave #11
+
+ wire run_rx, run_tx;
+ reg run_rx_d1;
+ always @(posedge dsp_clk)
+ run_rx_d1 <= run_rx;
+
+ atr_controller atr_controller
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
+ .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
+ .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+ assign s11_err = 0;
+ assign s11_rty = 0;
+
+ // //////////////////////////////////////////////////////////////////////////
+ // Time Sync, Slave #12
+
+ time_sync time_sync
+ (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
+ .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+ .sys_clk_i(dsp_clk),.master_time_o(master_time),
+ .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+ .int_o(pps_int) );
+ assign s12_err = 0;
+ assign s12_rty = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // DSP
+ wire [31:0] sample_rx, sample_tx;
+ wire strobe_rx, strobe_tx;
+
+ rx_control #(.FIFOSIZE(10)) rx_control
+ (.clk(dsp_clk), .rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .master_time(master_time),.overrun(overrun),
+ .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error),
+ .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
+ .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+ .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
+ .debug_rx(debug_rx) );
+
+ // dummy_rx dsp_core_rx
+ dsp_core_rx dsp_core_rx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+ .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+ .debug(debug_rx_dsp) );
+
+ tx_control #(.FIFOSIZE(10)) tx_control
+ (.clk(dsp_clk), .rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .master_time(master_time),.underrun(underrun),
+ .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
+ .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
+ .debug(debug_txc) );
+
+ dsp_core_tx dsp_core_tx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
+
+ assign dsp_rst = wb_rst;
+
+ // ///////////////////////////////////////////////////////////////////////////////////
+ // SERDES
+
+ serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+ .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error),
+ .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
+ .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+ .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
+ .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+ .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+ .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+ .debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+ // ///////////////////////////////////////////////////////////////////////////////////
+ // External RAM Interface
+
+ extram_interface extram_interface
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error),
+ .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop),
+ .wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error),
+ .wr_ready_i(wr3_ready),.wr_full_i(wr3_full),
+ .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
+ .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn) );
+
+
+ // /////////////////////////////////////////////////////////////////////////////////////////
+ // Debug Pins
+
+ // FIFO Level Debugging
+ reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug;
+
+ always @(posedge dsp_clk)
+ host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+ {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+ always @(posedge dsp_clk)
+ dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
+ always @(posedge dsp_clk)
+ eth_mac_debug <= {
+ // {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]},
+ // {underrun, overrun, debug_mac0[13:0] },
+ {debug_txc[15:0]},
+ {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+
+ wire debug_mux;
+ setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(debug_mux),.changed());
+
+ assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+
+ // Assign various commonly used debug buses.
+ /*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+
+ wire [31:0] debug_time = {uart_tx_o, 7'b0,
+ irq[7:0],
+ 6'b0, GMII_RX_DV, GMII_TX_EN,
+ 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+
+ wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack,
+ irq[7:0],
+ proc_int, 7'b0 };
+
+ wire [31:0] debug_eth =
+ {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+ {8'd0},
+ {8'd0},
+ {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
+
+ assign debug_serdes0 = { { rd0_dat[7:0] },
+ { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
+ { ser_t[15:8] },
+ { ser_t[7:0] } };
+
+ assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+ { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+ { ser_r[15:8] },
+ { ser_r[7:0] } };
+
+ assign debug_gpio_1 = {uart_tx_o,7'd0,
+ 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+ debug_txc[15:0]};
+ assign debug_gpio_1 = debug_rx;
+ assign debug_gpio_1 = debug_serdes1;
+ assign debug_gpio_1 = debug_eth;
+
+ */
+
+ // Choose actual debug buses
+ assign debug_clk[0] = wb_clk;
+ assign debug_clk[1] = dsp_clk;
+
+ //assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+ // {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+ //assign debug = debug_tx_dsp;
+ //assign debug = debug_serdes0;
+
+ assign debug_gpio_0 = 0; // debug_serdes1;
+ assign debug_gpio_1 = eth_mac_debug;
+
+endmodule // u2_core
diff --git a/top/u2_fpga/Makefile b/top/u2_fpga/Makefile
new file mode 100644
index 000000000..b3245d883
--- /dev/null
+++ b/top/u2_fpga/Makefile
@@ -0,0 +1,129 @@
+FILENAME=u2_fpga_top
+PARTNUM=xc3s1500-5fg456
+
+all: project command xst ngd ncd ncd2 bit
+
+xst:
+ xst -ifn ${FILENAME}.cmd -ofn xst.log
+
+ngd:
+ ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
+
+ncd:
+ rm -rf ${FILENAME}.ncd
+ map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
+
+# Place and route ncd file into new ncd file
+ncd2:
+ par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
+
+bit:
+ bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
+
+clean:
+ @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
+ *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
+ *.blc *.bld *.ise_ISE_Backup *~ \
+ *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
+ *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
+ *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
+ output.dat coregen.log *.ngo *.log ${FILENAME}.map \
+ ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
+
+command:
+ rm -rf ${FILENAME}.cmd
+ @echo "identification" >> ${FILENAME}.cmd
+ @echo "status" >> ${FILENAME}.cmd
+ @echo "time short" >> ${FILENAME}.cmd
+ @echo "memory on" >> ${FILENAME}.cmd
+ @echo "run " >> ${FILENAME}.cmd
+ @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
+ @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
+ @echo "-ifmt Verilog " >> ${FILENAME}.cmd
+ @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
+ @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
+ @echo "-bufg 6" >> ${FILENAME}.cmd
+ @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
+
+project:
+ rm -f ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj
+ @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj
+ @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj
+ @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj
diff --git a/top/u2_fpga/u2_fpga.ise b/top/u2_fpga/u2_fpga.ise
new file mode 100644
index 000000000..f90caf024
--- /dev/null
+++ b/top/u2_fpga/u2_fpga.ise
Binary files differ
diff --git a/top/u2_fpga/u2_fpga.ucf b/top/u2_fpga/u2_fpga.ucf
new file mode 100755
index 000000000..5d2124819
--- /dev/null
+++ b/top/u2_fpga/u2_fpga.ucf
@@ -0,0 +1,341 @@
+NET "adc_a[0]" LOC = "A14" ;
+NET "adc_a[10]" LOC = "D20" ;
+NET "adc_a[11]" LOC = "D19" ;
+NET "adc_a[12]" LOC = "D21" ;
+NET "adc_a[13]" LOC = "E18" ;
+NET "adc_a[1]" LOC = "B14" ;
+NET "adc_a[2]" LOC = "C13" ;
+NET "adc_a[3]" LOC = "D13" ;
+NET "adc_a[4]" LOC = "A13" ;
+NET "adc_a[5]" LOC = "B13" ;
+NET "adc_a[6]" LOC = "E12" ;
+NET "adc_a[7]" LOC = "C22" ;
+NET "adc_a[8]" LOC = "C20" ;
+NET "adc_a[9]" LOC = "C21" ;
+NET "adc_b[0]" LOC = "A12" ;
+NET "adc_b[10]" LOC = "D18" ;
+NET "adc_b[11]" LOC = "B18" ;
+NET "adc_b[12]" LOC = "D17" ;
+NET "adc_b[13]" LOC = "E17" ;
+NET "adc_b[1]" LOC = "E16" ;
+NET "adc_b[2]" LOC = "F12" ;
+NET "adc_b[3]" LOC = "F13" ;
+NET "adc_b[4]" LOC = "F16" ;
+NET "adc_b[5]" LOC = "F17" ;
+NET "adc_b[6]" LOC = "C19" ;
+NET "adc_b[7]" LOC = "B20" ;
+NET "adc_b[8]" LOC = "B19" ;
+NET "adc_b[9]" LOC = "C18" ;
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_TXD[0]" LOC = "W14" ;
+NET "GMII_TXD[1]" LOC = "AA20" ;
+NET "GMII_TXD[2]" LOC = "AB20" ;
+NET "GMII_TXD[3]" LOC = "Y18" ;
+NET "GMII_TXD[4]" LOC = "AA18" ;
+NET "GMII_TXD[5]" LOC = "AB18" ;
+NET "GMII_TXD[6]" LOC = "V17" ;
+NET "GMII_TXD[7]" LOC = "W17" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "RAM_A[0]" LOC = "N22" ;
+NET "RAM_A[10]" LOC = "P18" ;
+NET "RAM_A[11]" LOC = "R19" ;
+NET "RAM_A[12]" LOC = "P19" ;
+NET "RAM_A[13]" LOC = "R21" ;
+NET "RAM_A[14]" LOC = "R22" ;
+NET "RAM_A[15]" LOC = "T19" ;
+NET "RAM_A[16]" LOC = "T20" ;
+NET "RAM_A[17]" LOC = "U20" ;
+NET "RAM_A[18]" LOC = "W19" ;
+NET "RAM_A[1]" LOC = "N20" ;
+NET "RAM_A[2]" LOC = "T21" ;
+NET "RAM_A[3]" LOC = "M22" ;
+NET "RAM_A[4]" LOC = "N19" ;
+NET "RAM_A[5]" LOC = "N17" ;
+NET "RAM_A[6]" LOC = "N18" ;
+NET "RAM_A[7]" LOC = "P21" ;
+NET "RAM_A[8]" LOC = "P22" ;
+NET "RAM_A[9]" LOC = "P17" ;
+NET "RAM_D[0]" LOC = "Y21" ;
+NET "RAM_D[10]" LOC = "V22" ;
+NET "RAM_D[11]" LOC = "V21" ;
+NET "RAM_D[12]" LOC = "T17" ;
+NET "RAM_D[13]" LOC = "U18" ;
+NET "RAM_D[14]" LOC = "U21" ;
+NET "RAM_D[15]" LOC = "R18" ;
+NET "RAM_D[16]" LOC = "T18" ;
+NET "RAM_D[17]" LOC = "T22" ;
+NET "RAM_D[1]" LOC = "Y20" ;
+NET "RAM_D[2]" LOC = "Y19" ;
+NET "RAM_D[3]" LOC = "W22" ;
+NET "RAM_D[4]" LOC = "Y22" ;
+NET "RAM_D[5]" LOC = "V19" ;
+NET "RAM_D[6]" LOC = "W21" ;
+NET "RAM_D[7]" LOC = "W20" ;
+NET "RAM_D[8]" LOC = "U19" ;
+NET "RAM_D[9]" LOC = "V20" ;
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_t[0]" LOC = "V7" ;
+NET "ser_t[10]" LOC = "AA6" ;
+NET "ser_t[11]" LOC = "Y6" ;
+NET "ser_t[12]" LOC = "W8" ;
+NET "ser_t[13]" LOC = "V8" ;
+NET "ser_t[14]" LOC = "AB8" ;
+NET "ser_t[15]" LOC = "AA8" ;
+NET "ser_t[1]" LOC = "V10" ;
+NET "ser_t[2]" LOC = "AB4" ;
+NET "ser_t[3]" LOC = "AA4" ;
+NET "ser_t[4]" LOC = "Y5" ;
+NET "ser_t[5]" LOC = "W5" ;
+NET "ser_t[6]" LOC = "AB5" ;
+NET "ser_t[7]" LOC = "AA5" ;
+NET "ser_t[8]" LOC = "W6" ;
+NET "ser_t[9]" LOC = "V6" ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_oen_a" LOC = "E19" ;
+NET "adc_oen_b" LOC = "C17" ;
+NET "adc_ovf_a" LOC = "F18" ;
+NET "adc_ovf_b" LOC = "B17" ;
+NET "adc_pdn_a" LOC = "E20" ;
+NET "adc_pdn_b" LOC = "D15" ;
+NET "clk_fpga_n" LOC = "B11" ;
+NET "clk_fpga_p" LOC = "A11" ;
+NET "clk_func" LOC = "C12" ;
+NET "clk_status" LOC = "B12" ;
+NET "clk_to_mac" LOC = "AB12" ;
+NET "cpld_clk" LOC = "AB14" ;
+NET "cpld_din" LOC = "AA14" ;
+NET "cpld_done" LOC = "V12" ;
+NET "cpld_mode" LOC = "U12" ;
+NET "cpld_start" LOC = "AA9" ;
+NET "exp_pps_in_n" LOC = "V4" ;
+NET "exp_pps_in_p" LOC = "V3" ;
+NET "exp_pps_out_n" LOC = "V2" ;
+NET "exp_pps_out_p" LOC = "V1" ;
+NET "GMII_COL" LOC = "U16" ;
+NET "GMII_CRS" LOC = "U17" ;
+NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_RX_CLK" LOC = "W16" ;
+NET "GMII_RX_DV" LOC = "AB16" ;
+NET "GMII_RX_ER" LOC = "AA16" ;
+NET "GMII_TX_CLK" LOC = "W13" ;
+NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "led1" LOC = "V11" ;
+NET "led2" LOC = "Y12" ;
+NET "MDC" LOC = "V18" ;
+NET "MDIO" LOC = "Y16" | PULLUP ;
+NET "PHY_CLK" LOC = "V15" ;
+NET "PHY_INTn" LOC = "AB13" ;
+NET "PHY_RESETn" LOC = "AA19" ;
+NET "pps_in" LOC = "Y11" ;
+NET "RAM_CE1n" LOC = "N21" ;
+NET "RAM_CENn" LOC = "M18" ;
+NET "RAM_CLK" LOC = "M17" ;
+NET "RAM_LDn" LOC = "M21" ;
+NET "RAM_OEn" LOC = "M19" ;
+NET "RAM_WEn" LOC = "M20" ;
+NET "SCL" LOC = "A7" ;
+NET "SCL_force" LOC = "E8" ;
+NET "sclk" LOC = "K5" ;
+NET "sclk_rx_adc" LOC = "J17" ;
+NET "sclk_rx_dac" LOC = "J19" ;
+NET "sclk_rx_db" LOC = "F19" ;
+NET "sclk_tx_adc" LOC = "H1" ;
+NET "sclk_tx_dac" LOC = "J5" ;
+NET "sclk_tx_db" LOC = "D3" ;
+NET "SDA" LOC = "D8" ;
+NET "SDA_force" LOC = "C11" ;
+NET "sdi" LOC = "J1" ;
+NET "sdi_rx_adc" LOC = "H22" ;
+NET "sdi_rx_dac" LOC = "J21" ;
+NET "sdi_rx_db" LOC = "H19" ;
+NET "sdi_tx_adc" LOC = "J4" ;
+NET "sdi_tx_dac" LOC = "J6" ;
+NET "sdi_tx_db" LOC = "G4" ;
+NET "sdo" LOC = "J2" ;
+NET "sdo_rx_adc" LOC = "H21" ;
+NET "sdo_rx_db" LOC = "G20" ;
+NET "sdo_tx_adc" LOC = "H2" ;
+NET "sdo_tx_db" LOC = "G3" ;
+NET "sen_clk" LOC = "K6" ;
+NET "sen_dac" LOC = "L1" ;
+NET "sen_rx_adc" LOC = "H18" ;
+NET "sen_rx_dac" LOC = "J18" ;
+NET "sen_rx_db" LOC = "D22" ;
+NET "sen_tx_adc" LOC = "G2" ;
+NET "sen_tx_dac" LOC = "H4" ;
+NET "sen_tx_db" LOC = "C1" ;
+NET "ser_enable" LOC = "W11" ;
+NET "ser_loopen" LOC = "Y4" ;
+NET "ser_prbsen" LOC = "AA3" ;
+NET "ser_rklsb" LOC = "V9" ;
+NET "ser_rkmsb" LOC = "Y10" ;
+NET "ser_rx_clk" LOC = "AA11" ;
+NET "ser_rx_en" LOC = "AB9" ;
+NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/top/u2_fpga/u2_fpga_top.prj b/top/u2_fpga/u2_fpga_top.prj
new file mode 100644
index 000000000..544415f4d
--- /dev/null
+++ b/top/u2_fpga/u2_fpga_top.prj
@@ -0,0 +1,102 @@
+verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
+verilog work "../../control_lib/ram_2port.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/longfifo.v"
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/cordic_stage.v"
+verilog work "../../sdr_lib/cic_int_shifter.v"
+verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
+verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/cascadefifo2.v"
+verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../timing/time_sender.v"
+verilog work "../../timing/time_receiver.v"
+verilog work "../../serdes/serdes_tx.v"
+verilog work "../../serdes/serdes_rx.v"
+verilog work "../../serdes/serdes_fc_tx.v"
+verilog work "../../serdes/serdes_fc_rx.v"
+verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_interp.v"
+verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Phy_int.v"
+verilog work "../../eth/rtl/verilog/MAC_tx.v"
+verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
+verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/mux8.v"
+verilog work "../../control_lib/mux4.v"
+verilog work "../../control_lib/icache.v"
+verilog work "../../control_lib/dpram32.v"
+verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/dcache.v"
+verilog work "../../control_lib/buffer_int.v"
+verilog work "../../timing/timer.v"
+verilog work "../../timing/time_sync.v"
+verilog work "../../serdes/serdes.v"
+verilog work "../../sdr_lib/tx_control.v"
+verilog work "../../sdr_lib/rx_control.v"
+verilog work "../../sdr_lib/dsp_core_tx.v"
+verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
+verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../eth/rtl/verilog/MAC_top.v"
+verilog work "../../eth/mac_txfifo_int.v"
+verilog work "../../eth/mac_rxfifo_int.v"
+verilog work "../../control_lib/wb_readback_mux.v"
+verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/system_control.v"
+verilog work "../../control_lib/settings_bus.v"
+verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/ram_harv_cache.v"
+verilog work "../../control_lib/nsgpio.v"
+verilog work "../../control_lib/extram_interface.v"
+verilog work "../../control_lib/buffer_pool.v"
+verilog work "../../control_lib/atr_controller.v"
+verilog work "../u2_basic/u2_basic.v"
+verilog work "u2_fpga_top.v"
diff --git a/top/u2_fpga/u2_fpga_top.v b/top/u2_fpga/u2_fpga_top.v
new file mode 100644
index 000000000..63798a0c8
--- /dev/null
+++ b/top/u2_fpga/u2_fpga_top.v
@@ -0,0 +1,393 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_fpga_top
+ (
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+ // I2C
+ inout SCL,
+ inout SDA,
+ input SCL_force,
+ input SDA_force,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ output sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ output sen_tx_db,
+ output sclk_tx_db,
+ input sdo_tx_db,
+ output sdi_tx_db,
+
+ output sen_tx_adc,
+ output sclk_tx_adc,
+ input sdo_tx_adc,
+ output sdi_tx_adc,
+
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ // FPGA-specific pins connections
+ wire aux_clk = PHY_CLK;
+ //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
+ wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire
+
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge aux_clk)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+ wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_muxed),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire led1_int, led2_int;
+ assign led1 = ~led1_int;
+ assign led2 = ~led2_int;
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_basic u2_basic(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .led1 (led1_int),
+ .led2 (led2_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (),
+ .uart_rx_i (),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2_fpga_top
diff --git a/top/u2_rev2/Makefile b/top/u2_rev2/Makefile
new file mode 100644
index 000000000..a5969d62e
--- /dev/null
+++ b/top/u2_rev2/Makefile
@@ -0,0 +1,257 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev2
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/extram_interface.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev2/u2_rev2.ucf \
+top/u2_rev2/u2_rev2.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+#export TRANSLATE_PROPERTIES := \
+#"Macro Search Path" "$(SOURCE_ROOT)coregen/"
+#export TRANSLATE_PROPERTIES := \
+#"Macro Search Path" "$(shell pwd)/../../coregen/"
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "../../coregen/"
+
+QUICK_MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+quick:
+ PROCESS_RUN="Generate Programming File" MAP_PROPERTIES='$(QUICK_MAP_PROPERTIES)' $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/top/u2_rev2/u2_rev2.ucf b/top/u2_rev2/u2_rev2.ucf
new file mode 100644
index 000000000..e18dc6f17
--- /dev/null
+++ b/top/u2_rev2/u2_rev2.ucf
@@ -0,0 +1,337 @@
+NET "leds[0]" LOC = "F7" ;
+NET "leds[1]" LOC = "E5" ;
+NET "leds[2]" LOC = "B7" ;
+NET "leds[3]" LOC = "C11" ;
+NET "leds[4]" LOC = "AB19" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "uart_tx_o" LOC = "C7" ;
+NET "uart_rx_i" LOC = "A3" ;
+NET "exp_pps_in_p" LOC = "V3" ;
+NET "exp_pps_in_n" LOC = "V4" ;
+NET "exp_pps_out_p" LOC = "V1" ;
+NET "exp_pps_out_n" LOC = "V2" ;
+NET "GMII_COL" LOC = "U16" ;
+NET "GMII_CRS" LOC = "U17" ;
+NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_CLK" LOC = "W13" ;
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_RX_CLK" LOC = "W16" ;
+NET "GMII_RX_DV" LOC = "AB16" ;
+NET "GMII_RX_ER" LOC = "AA16" ;
+NET "MDIO" LOC = "Y16" |PULLUP ;
+NET "MDC" LOC = "V18" ;
+NET "PHY_INTn" LOC = "AB13" ;
+NET "PHY_RESETn" LOC = "AA19" ;
+NET "PHY_CLK" LOC = "V15" ;
+NET "RAM_D[0]" LOC = "N20" ;
+NET "RAM_D[1]" LOC = "N21" ;
+NET "RAM_D[2]" LOC = "N22" ;
+NET "RAM_D[3]" LOC = "M17" ;
+NET "RAM_D[4]" LOC = "M18" ;
+NET "RAM_D[5]" LOC = "M19" ;
+NET "RAM_D[6]" LOC = "M20" ;
+NET "RAM_D[7]" LOC = "M21" ;
+NET "RAM_D[8]" LOC = "M22" ;
+NET "RAM_D[9]" LOC = "Y22" ;
+NET "RAM_D[10]" LOC = "Y21" ;
+NET "RAM_D[11]" LOC = "Y20" ;
+NET "RAM_D[12]" LOC = "Y19" ;
+NET "RAM_D[13]" LOC = "W22" ;
+NET "RAM_D[14]" LOC = "W21" ;
+NET "RAM_D[15]" LOC = "W20" ;
+NET "RAM_D[16]" LOC = "W19" ;
+NET "RAM_D[17]" LOC = "V22" ;
+NET "RAM_A[0]" LOC = "U21" ;
+NET "RAM_A[1]" LOC = "T19" ;
+NET "RAM_A[2]" LOC = "V21" ;
+NET "RAM_A[3]" LOC = "V20" ;
+NET "RAM_A[4]" LOC = "T20" ;
+NET "RAM_A[5]" LOC = "T21" ;
+NET "RAM_A[6]" LOC = "T22" ;
+NET "RAM_A[7]" LOC = "T18" ;
+NET "RAM_A[8]" LOC = "R18" ;
+NET "RAM_A[9]" LOC = "P19" ;
+NET "RAM_A[10]" LOC = "P21" ;
+NET "RAM_A[11]" LOC = "P22" ;
+NET "RAM_A[12]" LOC = "N19" ;
+NET "RAM_A[13]" LOC = "N17" ;
+NET "RAM_A[14]" LOC = "N18" ;
+NET "RAM_A[15]" LOC = "T17" ;
+NET "RAM_A[16]" LOC = "U19" ;
+NET "RAM_A[17]" LOC = "U18" ;
+NET "RAM_A[18]" LOC = "V19" ;
+NET "RAM_CE1n" LOC = "U20" ;
+NET "RAM_CENn" LOC = "P18" ;
+NET "RAM_CLK" LOC = "P17" ;
+NET "RAM_WEn" LOC = "R22" ;
+NET "RAM_OEn" LOC = "R21" ;
+NET "RAM_LDn" LOC = "R19" ;
+NET "ser_enable" LOC = "W11" ;
+NET "ser_prbsen" LOC = "AA3" ;
+NET "ser_loopen" LOC = "Y4" ;
+NET "ser_rx_en" LOC = "AB9" ;
+NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_rx_clk" LOC = "AA11" ;
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_rklsb" LOC = "V9" ;
+NET "ser_rkmsb" LOC = "Y10" ;
+NET "cpld_start" LOC = "AA9" ;
+NET "cpld_mode" LOC = "U12" ;
+NET "cpld_done" LOC = "V12" ;
+NET "cpld_din" LOC = "AA14" ;
+NET "cpld_clk" LOC = "AB14" ;
+NET "cpld_detached" LOC = "V11" ;
+NET "cpld_init_b" LOC = "W12" ;
+NET "cpld_misc" LOC = "Y12" ;
+NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a" LOC = "F18" ;
+NET "adc_oen_a" LOC = "E19" ;
+NET "adc_pdn_a" LOC = "E20" ;
+NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b" LOC = "B17" ;
+NET "adc_oen_b" LOC = "C17" ;
+NET "adc_pdn_b" LOC = "D15" ;
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_lock" LOC = "D6" ;
+NET "SCL" LOC = "A7" ;
+NET "SDA" LOC = "D8" ;
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "clk_func" LOC = "C12" ;
+NET "clk_status" LOC = "B12" ;
+NET "clk_fpga_p" LOC = "A11" ;
+NET "clk_fpga_n" LOC = "B11" ;
+NET "clk_to_mac" LOC = "AB12" ;
+NET "pps_in" LOC = "Y11" ;
+NET "sclk" LOC = "K5" ;
+NET "sen_clk" LOC = "K6" ;
+NET "sen_dac" LOC = "L1" ;
+NET "sdi" LOC = "J1" ;
+NET "sdo" LOC = "J2" ;
+NET "sen_tx_db" LOC = "C1" ;
+NET "sclk_tx_db" LOC = "D3" ;
+NET "sdo_tx_db" LOC = "G3" ;
+NET "sdi_tx_db" LOC = "G4" ;
+NET "sen_tx_adc" LOC = "G2" ;
+NET "sclk_tx_adc" LOC = "H1" ;
+NET "sdo_tx_adc" LOC = "H2" ;
+NET "sdi_tx_adc" LOC = "J4" ;
+NET "sen_tx_dac" LOC = "H4" ;
+NET "sclk_tx_dac" LOC = "J5" ;
+NET "sdi_tx_dac" LOC = "J6" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "sen_rx_db" LOC = "D22" ;
+NET "sclk_rx_db" LOC = "F19" ;
+NET "sdo_rx_db" LOC = "G20" ;
+NET "sdi_rx_db" LOC = "H19" ;
+NET "sen_rx_adc" LOC = "H18" ;
+NET "sclk_rx_adc" LOC = "J17" ;
+NET "sdo_rx_adc" LOC = "H21" ;
+NET "sdi_rx_adc" LOC = "H22" ;
+NET "sen_rx_dac" LOC = "J18" ;
+NET "sclk_rx_dac" LOC = "J19" ;
+NET "sdi_rx_dac" LOC = "J21" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+#NET "dsp_clk" TNM_NET = "dsp_clk";
+#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+#NET "wb_clk" TNM_NET = "wb_clk";
+#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/top/u2_rev2/u2_rev2.v b/top/u2_rev2/u2_rev2.v
new file mode 100644
index 000000000..65d3ad656
--- /dev/null
+++ b/top/u2_rev2/u2_rev2.v
@@ -0,0 +1,413 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev2
+ (
+ // Misc, debug
+ output [4:0] leds,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+ output uart_tx_o,
+ input uart_rx_i,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+ input cpld_detached,// V11 unused
+ output cpld_init_b, // W12 unused dual purpose
+ input cpld_misc, // Y12 unused
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output reg [15:0] dac_a,
+ output reg [15:0] dac_b,
+ input dac_lock, // unused for now
+
+ // I2C
+ inout SCL,
+ inout SDA,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ output sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ output sen_tx_db,
+ output sclk_tx_db,
+ input sdo_tx_db,
+ output sdi_tx_db,
+
+ output sen_tx_adc,
+ output sclk_tx_adc,
+ input sdo_tx_adc,
+ output sdi_tx_adc,
+
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ assign cpld_init_b = 0;
+ // FPGA-specific pins connections
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+ wire clk90, clk180, clk270;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge clk_fpga)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+ reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg1 <= adc_a;
+ adc_b_reg1 <= adc_b;
+ adc_ovf_a_reg1 <= adc_ovf_a;
+ adc_ovf_b_reg1 <= adc_ovf_b;
+ end
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg2 <= adc_a_reg1;
+ adc_b_reg2 <= adc_b_reg1;
+ adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+ adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+ end // always @ (posedge dsp_clk)
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_fpga),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(clk90),
+ .CLK180(clk180),
+ .CLK270(clk270),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire [4:0] leds_int;
+ assign leds = 5'b01111 ^ leds_int; // all except eth are active-low
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ wire [15:0] dac_a_int, dac_b_int;
+ always @(negedge dsp_clk) dac_a <= dac_a_int;
+ always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_core #(.RAM_SIZE(32768))
+ u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a_reg2),
+ .adc_ovf_a (adc_ovf_a_reg2),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b_reg2),
+ .adc_ovf_b (adc_ovf_b_reg2),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a_int),
+ .dac_b (dac_b_int),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ .uart_rx_i (uart_rx_i),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2_rev2
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
new file mode 100644
index 000000000..897b68d68
--- /dev/null
+++ b/top/u2_rev3/Makefile
@@ -0,0 +1,244 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/extram_interface.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/top/u2_rev3/u2_rev3.ucf b/top/u2_rev3/u2_rev3.ucf
new file mode 100644
index 000000000..255a298ac
--- /dev/null
+++ b/top/u2_rev3/u2_rev3.ucf
@@ -0,0 +1,333 @@
+NET "leds[0]" LOC = "E8" ;
+NET "leds[1]" LOC = "F7" ;
+NET "leds[2]" LOC = "E5" ;
+NET "leds[3]" LOC = "B7" ;
+NET "leds[4]" LOC = "C11" ;
+NET "leds[5]" LOC = "AB19" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "uart_tx_o" LOC = "C7" ;
+NET "uart_rx_i" LOC = "A3" ;
+NET "exp_pps_in_p" LOC = "V3" ;
+NET "exp_pps_in_n" LOC = "V4" ;
+NET "exp_pps_out_p" LOC = "V1" ;
+NET "exp_pps_out_n" LOC = "V2" ;
+NET "GMII_COL" LOC = "U16" ;
+NET "GMII_CRS" LOC = "U17" ;
+NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "GMII_TX_CLK" LOC = "W13" ;
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_RX_CLK" LOC = "AA12" ;
+NET "GMII_RX_DV" LOC = "AB16" ;
+NET "GMII_RX_ER" LOC = "AA16" ;
+NET "MDIO" LOC = "Y16" |PULLUP ;
+NET "MDC" LOC = "V18" ;
+NET "PHY_INTn" LOC = "AB13" ;
+NET "PHY_RESETn" LOC = "AA19" ;
+NET "PHY_CLK" LOC = "V15" ;
+NET "RAM_D[0]" LOC = "N20" ;
+NET "RAM_D[1]" LOC = "N21" ;
+NET "RAM_D[2]" LOC = "N22" ;
+NET "RAM_D[3]" LOC = "M17" ;
+NET "RAM_D[4]" LOC = "M18" ;
+NET "RAM_D[5]" LOC = "M19" ;
+NET "RAM_D[6]" LOC = "M20" ;
+NET "RAM_D[7]" LOC = "M21" ;
+NET "RAM_D[8]" LOC = "M22" ;
+NET "RAM_D[9]" LOC = "Y22" ;
+NET "RAM_D[10]" LOC = "Y21" ;
+NET "RAM_D[11]" LOC = "Y20" ;
+NET "RAM_D[12]" LOC = "Y19" ;
+NET "RAM_D[13]" LOC = "W22" ;
+NET "RAM_D[14]" LOC = "W21" ;
+NET "RAM_D[15]" LOC = "W20" ;
+NET "RAM_D[16]" LOC = "W19" ;
+NET "RAM_D[17]" LOC = "V22" ;
+NET "RAM_A[0]" LOC = "U21" ;
+NET "RAM_A[1]" LOC = "T19" ;
+NET "RAM_A[2]" LOC = "V21" ;
+NET "RAM_A[3]" LOC = "V20" ;
+NET "RAM_A[4]" LOC = "T20" ;
+NET "RAM_A[5]" LOC = "T21" ;
+NET "RAM_A[6]" LOC = "T22" ;
+NET "RAM_A[7]" LOC = "T18" ;
+NET "RAM_A[8]" LOC = "R18" ;
+NET "RAM_A[9]" LOC = "P19" ;
+NET "RAM_A[10]" LOC = "P21" ;
+NET "RAM_A[11]" LOC = "P22" ;
+NET "RAM_A[12]" LOC = "N19" ;
+NET "RAM_A[13]" LOC = "N17" ;
+NET "RAM_A[14]" LOC = "N18" ;
+NET "RAM_A[15]" LOC = "T17" ;
+NET "RAM_A[16]" LOC = "U19" ;
+NET "RAM_A[17]" LOC = "U18" ;
+NET "RAM_A[18]" LOC = "V19" ;
+NET "RAM_CE1n" LOC = "U20" ;
+NET "RAM_CENn" LOC = "P18" ;
+NET "RAM_CLK" LOC = "P17" ;
+NET "RAM_WEn" LOC = "R22" ;
+NET "RAM_OEn" LOC = "R21" ;
+NET "RAM_LDn" LOC = "R19" ;
+NET "ser_enable" LOC = "W11" ;
+NET "ser_prbsen" LOC = "AA3" ;
+NET "ser_loopen" LOC = "Y4" ;
+NET "ser_rx_en" LOC = "AB9" ;
+NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "ser_rx_clk" LOC = "AA11" ;
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_rklsb" LOC = "V9" ;
+NET "ser_rkmsb" LOC = "Y10" ;
+NET "cpld_start" LOC = "AA9" ;
+NET "cpld_mode" LOC = "U12" ;
+NET "cpld_done" LOC = "V12" ;
+NET "cpld_din" LOC = "AA14" ;
+NET "cpld_clk" LOC = "AB14" ;
+NET "cpld_detached" LOC = "V11" ;
+NET "cpld_init_b" LOC = "W12" ;
+NET "cpld_misc" LOC = "Y12" ;
+NET "POR" LOC = "W18" ;
+NET "WDI" LOC = "W15" ;
+NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a" LOC = "F18" ;
+NET "adc_oen_a" LOC = "E19" ;
+NET "adc_pdn_a" LOC = "E20" ;
+NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b" LOC = "B17" ;
+NET "adc_oen_b" LOC = "C17" ;
+NET "adc_pdn_b" LOC = "D15" ;
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_lock" LOC = "D6" ;
+NET "SCL" LOC = "A7" ;
+NET "SDA" LOC = "D8" ;
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "clk_func" LOC = "C12" ;
+NET "clk_status" LOC = "B12" ;
+NET "clk_fpga_p" LOC = "A11" ;
+NET "clk_fpga_n" LOC = "B11" ;
+NET "clk_to_mac" LOC = "AB12" ;
+NET "pps_in" LOC = "K1" ;
+NET "sclk" LOC = "K5" ;
+NET "sen_clk" LOC = "K6" ;
+NET "sen_dac" LOC = "L1" ;
+NET "sdi" LOC = "J1" ;
+NET "sdo" LOC = "J2" ;
+NET "sen_tx_db" LOC = "C1" ;
+NET "sclk_tx_db" LOC = "D3" ;
+NET "sdo_tx_db" LOC = "G3" ;
+NET "sdi_tx_db" LOC = "G4" ;
+NET "sen_tx_adc" LOC = "G2" ;
+NET "sclk_tx_adc" LOC = "H1" ;
+NET "sdo_tx_adc" LOC = "H2" ;
+NET "sdi_tx_adc" LOC = "J4" ;
+NET "sen_tx_dac" LOC = "H4" ;
+NET "sclk_tx_dac" LOC = "J5" ;
+NET "sdi_tx_dac" LOC = "J6" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "sen_rx_db" LOC = "D22" ;
+NET "sclk_rx_db" LOC = "F19" ;
+NET "sdo_rx_db" LOC = "G20" ;
+NET "sdi_rx_db" LOC = "H19" ;
+NET "sen_rx_adc" LOC = "H18" ;
+NET "sclk_rx_adc" LOC = "J17" ;
+NET "sdo_rx_adc" LOC = "H21" ;
+NET "sdi_rx_adc" LOC = "H22" ;
+NET "sen_rx_dac" LOC = "J18" ;
+NET "sclk_rx_dac" LOC = "J19" ;
+NET "sdi_rx_dac" LOC = "J21" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/top/u2_rev3/u2_rev3.v b/top/u2_rev3/u2_rev3.v
new file mode 100644
index 000000000..c1a81a961
--- /dev/null
+++ b/top/u2_rev3/u2_rev3.v
@@ -0,0 +1,426 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev3
+ (
+ // Misc, debug
+ output [5:0] leds,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+ output uart_tx_o,
+ input uart_rx_i,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+ input cpld_detached,// V11 unused
+ output cpld_init_b, // W12 unused dual purpose
+ input cpld_misc, // Y12 unused
+
+ // Watchdog interface
+ input POR,
+ output WDI,
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output reg [15:0] dac_a,
+ output reg [15:0] dac_b,
+ input dac_lock, // unused for now
+
+ // I2C
+ inout SCL,
+ inout SDA,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ output sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ output sen_tx_db,
+ output sclk_tx_db,
+ input sdo_tx_db,
+ output sdi_tx_db,
+
+ output sen_tx_adc,
+ output sclk_tx_adc,
+ input sdo_tx_adc,
+ output sdi_tx_adc,
+
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ assign cpld_init_b = 0;
+ // FPGA-specific pins connections
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+ wire clk90, clk180, clk270;
+
+ // reset the watchdog continuously
+ reg [15:0] wd;
+ always @(posedge wb_clk)
+ if(POR)
+ wd <= 0;
+ else
+ wd <= wd + 1;
+ assign WDI = wd[15];
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge clk_fpga)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+ reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg1 <= adc_a;
+ adc_b_reg1 <= adc_b;
+ adc_ovf_a_reg1 <= adc_ovf_a;
+ adc_ovf_b_reg1 <= adc_ovf_b;
+ end
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg2 <= adc_a_reg1;
+ adc_b_reg2 <= adc_b_reg1;
+ adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+ adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+ end // always @ (posedge dsp_clk)
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_fpga),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(clk90),
+ .CLK180(clk180),
+ .CLK270(clk270),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire [5:0] leds_int;
+ assign leds = 6'b011111 ^ leds_int; // all except eth are active-low
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ wire [15:0] dac_a_int, dac_b_int;
+ always @(negedge dsp_clk) dac_a <= dac_a_int;
+ always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_core #(.RAM_SIZE(32768))
+ u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a_reg2),
+ .adc_ovf_a (adc_ovf_a_reg2),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b_reg2),
+ .adc_ovf_b (adc_ovf_b_reg2),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a_int),
+ .dac_b (dac_b_int),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ .uart_rx_i (uart_rx_i),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2_rev2
diff --git a/top/u2plus/u2plus.ucf b/top/u2plus/u2plus.ucf
new file mode 100755
index 000000000..3f71d0b1e
--- /dev/null
+++ b/top/u2plus/u2plus.ucf
@@ -0,0 +1,280 @@
+NET "leds[0]" LOC = "A17" ;
+NET "leds[1]" LOC = "B20" ;
+NET "leds[2]" LOC = "D13" ;
+NET "leds[3]" LOC = "A14" ;
+NET "leds[4]" LOC = "W15" ;
+NET "dipsw[0]" LOC = "C11" ;
+NET "dipsw[1]" LOC = "F12" ;
+NET "dipsw[2]" LOC = "E17" ;
+NET "dipsw[3]" LOC = "E10" ;
+NET "debug[0]" LOC = "AB19" ;
+NET "debug[1]" LOC = "AA19" ;
+NET "debug[2]" LOC = "U14" ;
+NET "debug[3]" LOC = "U15" ;
+NET "debug[4]" LOC = "AB17" ;
+NET "debug[5]" LOC = "AB18" ;
+NET "debug[6]" LOC = "Y13" ;
+NET "debug[7]" LOC = "W14" ;
+NET "debug[8]" LOC = "U13" ;
+NET "debug[9]" LOC = "AA15" ;
+NET "debug[10]" LOC = "AB14" ;
+NET "debug[11]" LOC = "Y8" ;
+NET "debug[12]" LOC = "Y9" ;
+NET "debug[13]" LOC = "V7" ;
+NET "debug[14]" LOC = "U8" ;
+NET "debug[15]" LOC = "V10" ;
+NET "debug[16]" LOC = "U9" ;
+NET "debug[17]" LOC = "AB7" ;
+NET "debug[18]" LOC = "AA8" ;
+NET "debug[19]" LOC = "W8" ;
+NET "debug[20]" LOC = "V8" ;
+NET "debug[21]" LOC = "AB5" ;
+NET "debug[22]" LOC = "AB6" ;
+NET "debug[23]" LOC = "AB4" ;
+NET "debug[24]" LOC = "AA4" ;
+NET "debug[25]" LOC = "W5" ;
+NET "debug[26]" LOC = "Y4" ;
+NET "debug[27]" LOC = "V11" ;
+NET "debug[28]" LOC = "U10" ;
+NET "debug[29]" LOC = "AB10" ;
+NET "debug[30]" LOC = "AA10" ;
+NET "debug[31]" LOC = "Y5" ;
+NET "debug_clk[0]" LOC = "V16" ;
+NET "debug_clk[1]" LOC = "U16" ;
+NET "uart_tx_o" LOC = "C19" ;
+NET "uart_rx_i" LOC = "A20" ;
+NET "exp_pps_in_p" LOC = "AA17" ;
+NET "exp_pps_in_n" LOC = "AB16" ;
+NET "exp_pps_out_p" LOC = "Y18" ;
+NET "exp_pps_out_n" LOC = "Y19" ;
+NET "GMII_COL" LOC = "J19" ;
+NET "GMII_CRS" LOC = "E22" ;
+NET "GMII_TXD[0]" LOC = "F22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[1]" LOC = "G18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[2]" LOC = "G17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[3]" LOC = "E20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[4]" LOC = "F21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[5]" LOC = "E19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[6]" LOC = "D20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TXD[7]" LOC = "D22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TX_EN" LOC = "D21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TX_ER" LOC = "F19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_GTX_CLK" LOC = "F18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "GMII_TX_CLK" LOC = "L20" ;
+NET "GMII_RXD[0]" LOC = "K17" ;
+NET "GMII_RXD[1]" LOC = "L18" ;
+NET "GMII_RXD[2]" LOC = "J22" ;
+NET "GMII_RXD[3]" LOC = "J21" ;
+NET "GMII_RXD[4]" LOC = "G20" ;
+NET "GMII_RXD[5]" LOC = "H21" ;
+NET "GMII_RXD[6]" LOC = "C21" ;
+NET "GMII_RXD[7]" LOC = "C22" ;
+NET "GMII_RX_CLK" LOC = "L21" ;
+NET "GMII_RX_DV" LOC = "G19" ;
+NET "GMII_RX_ER" LOC = "F20" ;
+NET "MDIO" LOC = "H22" | PULLUP ;
+NET "MDC" LOC = "G22" ;
+NET "PHY_INTn" LOC = "H20" ;
+NET "PHY_RESETn" LOC = "J17" ;
+NET "PHY_CLK" LOC = "M18" ;
+NET "clk_to_mac" LOC = "L17" ;
+NET "eth_led" LOC = "K16" ;
+NET "ser_enable" LOC = "Y21" ;
+NET "ser_prbsen" LOC = "U19" ;
+NET "ser_loopen" LOC = "U18" ;
+NET "ser_rx_en" LOC = "AA22" ;
+NET "ser_tx_clk" LOC = "J20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[0]" LOC = "U20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[1]" LOC = "R18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[2]" LOC = "P19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[3]" LOC = "U22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[4]" LOC = "P16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[5]" LOC = "N17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[6]" LOC = "P22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[7]" LOC = "R22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[8]" LOC = "N19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[9]" LOC = "N20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[10]" LOC = "M22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[11]" LOC = "N22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[12]" LOC = "K22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[13]" LOC = "L22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[14]" LOC = "K18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_t[15]" LOC = "K19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tklsb" LOC = "K20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_tkmsb" LOC = "H18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
+NET "ser_rx_clk" LOC = "N21" ;
+NET "ser_r[0]" LOC = "T22" ;
+NET "ser_r[1]" LOC = "W20" ;
+NET "ser_r[2]" LOC = "W21" ;
+NET "ser_r[3]" LOC = "U21" ;
+NET "ser_r[4]" LOC = "V22" ;
+NET "ser_r[5]" LOC = "P17" ;
+NET "ser_r[6]" LOC = "R17" ;
+NET "ser_r[7]" LOC = "P20" ;
+NET "ser_r[8]" LOC = "R21" ;
+NET "ser_r[9]" LOC = "V20" ;
+NET "ser_r[10]" LOC = "W19" ;
+NET "ser_r[11]" LOC = "T17" ;
+NET "ser_r[12]" LOC = "T18" ;
+NET "ser_r[13]" LOC = "Y22" ;
+NET "ser_r[14]" LOC = "W22" ;
+NET "ser_r[15]" LOC = "R20" ;
+NET "ser_rklsb" LOC = "R19" ;
+NET "ser_rkmsb" LOC = "T20" ;
+NET "adc_a[0]" LOC = "P3" ;
+NET "adc_a[1]" LOC = "N3" ;
+NET "adc_a[2]" LOC = "AA1" ;
+NET "adc_a[3]" LOC = "Y2" ;
+NET "adc_a[4]" LOC = "C5" ;
+NET "adc_a[5]" LOC = "E6" ;
+NET "adc_a[6]" LOC = "C7" ;
+NET "adc_a[7]" LOC = "E8" ;
+NET "adc_a[8]" LOC = "F8" ;
+NET "adc_a[9]" LOC = "A4" ;
+NET "adc_a[10]" LOC = "B4" ;
+NET "adc_a[11]" LOC = "C4" ;
+NET "adc_a[12]" LOC = "D5" ;
+NET "adc_a[13]" LOC = "A3" ;
+NET "adc_ovf_a" LOC = "B3" ;
+NET "adc_oen_a" LOC = "A6" ;
+NET "adc_pdn_a" LOC = "D7" ;
+NET "adc_b[0]" LOC = "J1" ;
+NET "adc_b[1]" LOC = "M1" ;
+NET "adc_b[2]" LOC = "P4" ;
+NET "adc_b[3]" LOC = "E1" ;
+NET "adc_b[4]" LOC = "D1" ;
+NET "adc_b[5]" LOC = "D4" ;
+NET "adc_b[6]" LOC = "D3" ;
+NET "adc_b[7]" LOC = "J7" ;
+NET "adc_b[8]" LOC = "J6" ;
+NET "adc_b[9]" LOC = "J4" ;
+NET "adc_b[10]" LOC = "J3" ;
+NET "adc_b[11]" LOC = "N4" ;
+NET "adc_b[12]" LOC = "M3" ;
+NET "adc_b[13]" LOC = "U3" ;
+NET "adc_ovf_b" LOC = "T3" ;
+NET "adc_oen_b" LOC = "B6" ;
+NET "adc_pdn_b" LOC = "A5" ;
+NET "dac_a[0]" LOC = "N5" ;
+NET "dac_a[1]" LOC = "N1" ;
+NET "dac_a[2]" LOC = "K2" ;
+NET "dac_a[3]" LOC = "K3" ;
+NET "dac_a[4]" LOC = "K6" ;
+NET "dac_a[5]" LOC = "L5" ;
+NET "dac_a[6]" LOC = "H2" ;
+NET "dac_a[7]" LOC = "K4" ;
+NET "dac_a[8]" LOC = "K5" ;
+NET "dac_a[9]" LOC = "G1" ;
+NET "dac_a[10]" LOC = "H1" ;
+NET "dac_a[11]" LOC = "H5" ;
+NET "dac_a[12]" LOC = "H6" ;
+NET "dac_a[13]" LOC = "E3" ;
+NET "dac_a[14]" LOC = "E4" ;
+NET "dac_a[15]" LOC = "G5" ;
+NET "dac_b[0]" LOC = "G6" ;
+NET "dac_b[1]" LOC = "F2" ;
+NET "dac_b[2]" LOC = "F1" ;
+NET "dac_b[3]" LOC = "H3" ;
+NET "dac_b[4]" LOC = "H4" ;
+NET "dac_b[5]" LOC = "F4" ;
+NET "dac_b[6]" LOC = "F5" ;
+NET "dac_b[7]" LOC = "C2" ;
+NET "dac_b[8]" LOC = "C1" ;
+NET "dac_b[9]" LOC = "F3" ;
+NET "dac_b[10]" LOC = "G3" ;
+NET "dac_b[11]" LOC = "M6" ;
+NET "dac_b[12]" LOC = "N7" ;
+NET "dac_b[13]" LOC = "L3" ;
+NET "dac_b[14]" LOC = "M2" ;
+NET "dac_b[15]" LOC = "K1" ;
+NET "dac_lock" LOC = "L1" ;
+NET "SCL" LOC = "B19" ;
+NET "SDA" LOC = "B17" ;
+NET "clk_en[0]" LOC = "AB20" ;
+NET "clk_en[1]" LOC = "AA20" ;
+NET "clk_sel[0]" LOC = "Y17" ;
+NET "clk_sel[1]" LOC = "Y16" ;
+NET "clk_func" LOC = "W13" ;
+NET "clk_status" LOC = "W18" ;
+NET "clk_fpga_p" LOC = "AA12" ;
+NET "clk_fpga_n" LOC = "AB12" ;
+NET "pps_in" LOC = "Y14" ;
+NET "POR" LOC = "AB15" ;
+NET "sclk" LOC = "AA14" ;
+NET "sen_clk" LOC = "AB13" ;
+NET "sdi" LOC = "V12" ;
+NET "sdo" LOC = "U12" ;
+NET "sen_dac" LOC = "W2" ;
+NET "sen_tx_db" LOC = "W3" ;
+NET "sen_tx_adc" LOC = "U5" ;
+NET "sen_tx_dac" LOC = "U4" ;
+NET "mosi_tx" LOC = "V4" ;
+NET "miso_dac" LOC = "M5" ;
+NET "miso_tx_db" LOC = "W1" ;
+NET "miso_tx_adc" LOC = "Y1" ;
+NET "sclk_tx" LOC = "V3" ;
+NET "sen_rx_db" LOC = "B9" ;
+NET "sclk_rx_db" LOC = "B8" ;
+NET "sdo_rx_db" LOC = "A10" ;
+NET "sdi_rx_db" LOC = "E12" ;
+NET "sen_rx_adc" LOC = "A9" ;
+NET "sclk_rx_adc" LOC = "A8" ;
+NET "sdo_rx_adc" LOC = "A12" ;
+NET "sdi_rx_adc" LOC = "A7" ;
+NET "sen_rx_dac" LOC = "E11" ;
+NET "sclk_rx_dac" LOC = "F10" ;
+NET "sdi_rx_dac" LOC = "E7" ;
+NET "io_tx[0]" LOC = "R3" ;
+NET "io_tx[1]" LOC = "T4" ;
+NET "io_tx[2]" LOC = "U2" ;
+NET "io_tx[3]" LOC = "V1" ;
+NET "io_tx[4]" LOC = "R5" ;
+NET "io_tx[5]" LOC = "T1" ;
+NET "io_tx[6]" LOC = "U1" ;
+NET "io_tx[7]" LOC = "T6" ;
+NET "io_tx[8]" LOC = "T5" ;
+NET "io_tx[9]" LOC = "R2" ;
+NET "io_tx[10]" LOC = "R1" ;
+NET "io_tx[11]" LOC = "P6" ;
+NET "io_tx[12]" LOC = "R6" ;
+NET "io_tx[13]" LOC = "P1" ;
+NET "io_tx[14]" LOC = "P2" ;
+NET "io_tx[15]" LOC = "N6" ;
+
+NET "io_rx[0]" LOC = "G8" ;
+NET "io_rx[1]" LOC = "F9" ;
+NET "io_rx[2]" LOC = "C8" ;
+NET "io_rx[3]" LOC = "D9" ;
+NET "io_rx[4]" LOC = "C6" ;
+NET "io_rx[5]" LOC = "D6" ;
+NET "io_rx[6]" LOC = "C9" ;
+NET "io_rx[7]" LOC = "D10" ;
+NET "io_rx[8]" LOC = "B11" ;
+NET "io_rx[9]" LOC = "A11" ;
+NET "io_rx[10]" LOC = "C13" ;
+NET "io_rx[11]" LOC = "C12" ;
+NET "io_rx[12]" LOC = "F14" ;
+NET "io_rx[13]" LOC = "F13" ;
+NET "io_rx[14]" LOC = "D14" ;
+NET "io_rx[15]" LOC = "A13" ;
+NET "flash_cs" LOC = "U7" ;
+NET "flash_clk" LOC = "V17" ;
+NET "flash_mosi" LOC = "V13" ;
+NET "flash_miso" LOC = "W17" ;
+
+
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
diff --git a/top/u2plus/u2plus.v b/top/u2plus/u2plus.v
new file mode 100644
index 000000000..e95445867
--- /dev/null
+++ b/top/u2plus/u2plus.v
@@ -0,0 +1,377 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2plus
+ (
+ // Misc, debug
+ output [4:0] leds, // LED4 is shared w/INIT_B
+ input [3:0] dipsw,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+ output uart_tx_o,
+ input uart_rx_i,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output reg [7:0] GMII_TXD,
+ output reg GMII_TX_EN,
+ output reg GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+ input clk_to_mac,
+ output eth_led,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+ input dac_lock, // unused for now
+
+ // I2C
+ inout SCL,
+ inout SDA,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p, // Diff
+ input clk_fpga_n, // Diff
+ input pps_in,
+ input POR,
+
+ // AD9510 SPI
+ output sclk,
+ output sen_clk,
+ output sdi,
+ input sdo,
+
+ // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
+ output sen_dac,
+ output sen_tx_db,
+ output sen_tx_adc,
+ output sen_tx_dac,
+ output mosi_tx,
+ input miso_dac,
+ input miso_tx_db,
+ input miso_tx_adc,
+ output sclk_tx,
+
+ // RX side SPI
+ output sen_rx_db,
+ output sclk_rx_db,
+ input sdo_rx_db,
+ output sdi_rx_db,
+
+ output sen_rx_adc,
+ output sclk_rx_adc,
+ input sdo_rx_adc,
+ output sdi_rx_adc,
+
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
+
+ // DB IO Pins
+ inout [15:0] io_tx,
+ inout [15:0] io_rx,
+
+ // SPI Flash
+ output flash_cs,
+ output flash_clk,
+ output flash_mosi,
+ input flash_miso
+ );
+
+ // FPGA-specific pins connections
+ wire aux_clk = PHY_CLK;
+
+ wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ reg [5:0] clock_ready_d;
+ always @(posedge aux_clk)
+ clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+ wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
+ wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+ wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+ assign adc_oen_a = ~adc_oe_a;
+ assign adc_oen_b = ~adc_oe_b;
+ assign adc_pdn_a = ~adc_on_a;
+ assign adc_pdn_b = ~adc_on_b;
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_muxed),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(dcm_rst),
+ .CLKDV(clk_div),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+ BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // LEDs are active low outputs
+ wire [4:0] leds_int;
+ assign leds = ~leds_int; // drive low to turn on leds
+
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+ wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+ wire [7:0] GMII_TXD_unreg;
+ wire GMII_GTX_CLK_int;
+
+ always @(posedge GMII_GTX_CLK_int)
+ begin
+ GMII_TX_EN <= GMII_TX_EN_unreg;
+ GMII_TX_ER <= GMII_TX_ER_unreg;
+ GMII_TXD <= GMII_TXD_unreg;
+ end
+
+ OFDDRRSE OFDDRRSE_gmii_inst
+ (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
+ .C0(GMII_GTX_CLK_int), // 0 degree clock input
+ .C1(~GMII_GTX_CLK_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+
+ wire ser_tklsb_unreg, ser_tkmsb_unreg;
+ wire [15:0] ser_t_unreg;
+ wire ser_tx_clk_int;
+
+ always @(posedge ser_tx_clk_int)
+ begin
+ ser_tklsb <= ser_tklsb_unreg;
+ ser_tkmsb <= ser_tkmsb_unreg;
+ ser_t <= ser_t_unreg;
+ end
+
+ assign ser_tx_clk = clk_fpga;
+
+ reg [15:0] ser_r_int;
+ reg ser_rklsb_int, ser_rkmsb_int;
+
+ always @(posedge ser_rx_clk)
+ begin
+ ser_r_int <= ser_r;
+ ser_rklsb_int <= ser_rklsb;
+ ser_rkmsb_int <= ser_rkmsb;
+ end
+
+ /*
+ OFDDRRSE OFDDRRSE_serdes_inst
+ (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
+ .C0(ser_tx_clk_int), // 0 degree clock input
+ .C1(~ser_tx_clk_int), // 180 degree clock input
+ .CE(1), // Clock enable input
+ .D0(0), // Posedge data input
+ .D1(1), // Negedge data input
+ .R(0), // Synchronous reset input
+ .S(0) // Synchronous preset input
+ );
+ */
+ u2_core u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D (RAM_D),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ //.uart_rx_i (uart_rx_i),
+ .uart_rx_i (),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
+
+endmodule // u2plus
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 18:27:13 +0000