diff options
Diffstat (limited to 'top/u2plus')
| -rwxr-xr-x | top/u2plus/u2plus.ucf | 280 | ||||
| -rw-r--r-- | top/u2plus/u2plus.v | 377 |
2 files changed, 657 insertions, 0 deletions
diff --git a/top/u2plus/u2plus.ucf b/top/u2plus/u2plus.ucf new file mode 100755 index 000000000..3f71d0b1e --- /dev/null +++ b/top/u2plus/u2plus.ucf @@ -0,0 +1,280 @@ +NET "leds[0]" LOC = "A17" ; +NET "leds[1]" LOC = "B20" ; +NET "leds[2]" LOC = "D13" ; +NET "leds[3]" LOC = "A14" ; +NET "leds[4]" LOC = "W15" ; +NET "dipsw[0]" LOC = "C11" ; +NET "dipsw[1]" LOC = "F12" ; +NET "dipsw[2]" LOC = "E17" ; +NET "dipsw[3]" LOC = "E10" ; +NET "debug[0]" LOC = "AB19" ; +NET "debug[1]" LOC = "AA19" ; +NET "debug[2]" LOC = "U14" ; +NET "debug[3]" LOC = "U15" ; +NET "debug[4]" LOC = "AB17" ; +NET "debug[5]" LOC = "AB18" ; +NET "debug[6]" LOC = "Y13" ; +NET "debug[7]" LOC = "W14" ; +NET "debug[8]" LOC = "U13" ; +NET "debug[9]" LOC = "AA15" ; +NET "debug[10]" LOC = "AB14" ; +NET "debug[11]" LOC = "Y8" ; +NET "debug[12]" LOC = "Y9" ; +NET "debug[13]" LOC = "V7" ; +NET "debug[14]" LOC = "U8" ; +NET "debug[15]" LOC = "V10" ; +NET "debug[16]" LOC = "U9" ; +NET "debug[17]" LOC = "AB7" ; +NET "debug[18]" LOC = "AA8" ; +NET "debug[19]" LOC = "W8" ; +NET "debug[20]" LOC = "V8" ; +NET "debug[21]" LOC = "AB5" ; +NET "debug[22]" LOC = "AB6" ; +NET "debug[23]" LOC = "AB4" ; +NET "debug[24]" LOC = "AA4" ; +NET "debug[25]" LOC = "W5" ; +NET "debug[26]" LOC = "Y4" ; +NET "debug[27]" LOC = "V11" ; +NET "debug[28]" LOC = "U10" ; +NET "debug[29]" LOC = "AB10" ; +NET "debug[30]" LOC = "AA10" ; +NET "debug[31]" LOC = "Y5" ; +NET "debug_clk[0]" LOC = "V16" ; +NET "debug_clk[1]" LOC = "U16" ; +NET "uart_tx_o" LOC = "C19" ; +NET "uart_rx_i" LOC = "A20" ; +NET "exp_pps_in_p" LOC = "AA17" ; +NET "exp_pps_in_n" LOC = "AB16" ; +NET "exp_pps_out_p" LOC = "Y18" ; +NET "exp_pps_out_n" LOC = "Y19" ; +NET "GMII_COL" LOC = "J19" ; +NET "GMII_CRS" LOC = "E22" ; +NET "GMII_TXD[0]" LOC = "F22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "G18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "G17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "E20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "F21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "E19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "D20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "D22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_EN" LOC = "D21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_ER" LOC = "F19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "F18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "L20" ; +NET "GMII_RXD[0]" LOC = "K17" ; +NET "GMII_RXD[1]" LOC = "L18" ; +NET "GMII_RXD[2]" LOC = "J22" ; +NET "GMII_RXD[3]" LOC = "J21" ; +NET "GMII_RXD[4]" LOC = "G20" ; +NET "GMII_RXD[5]" LOC = "H21" ; +NET "GMII_RXD[6]" LOC = "C21" ; +NET "GMII_RXD[7]" LOC = "C22" ; +NET "GMII_RX_CLK" LOC = "L21" ; +NET "GMII_RX_DV" LOC = "G19" ; +NET "GMII_RX_ER" LOC = "F20" ; +NET "MDIO" LOC = "H22" | PULLUP ; +NET "MDC" LOC = "G22" ; +NET "PHY_INTn" LOC = "H20" ; +NET "PHY_RESETn" LOC = "J17" ; +NET "PHY_CLK" LOC = "M18" ; +NET "clk_to_mac" LOC = "L17" ; +NET "eth_led" LOC = "K16" ; +NET "ser_enable" LOC = "Y21" ; +NET "ser_prbsen" LOC = "U19" ; +NET "ser_loopen" LOC = "U18" ; +NET "ser_rx_en" LOC = "AA22" ; +NET "ser_tx_clk" LOC = "J20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[0]" LOC = "U20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[1]" LOC = "R18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[2]" LOC = "P19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[3]" LOC = "U22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[4]" LOC = "P16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[5]" LOC = "N17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[6]" LOC = "P22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[7]" LOC = "R22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[8]" LOC = "N19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[9]" LOC = "N20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[10]" LOC = "M22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[11]" LOC = "N22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[12]" LOC = "K22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[13]" LOC = "L22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[14]" LOC = "K18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[15]" LOC = "K19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tklsb" LOC = "K20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tkmsb" LOC = "H18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_rx_clk" LOC = "N21" ; +NET "ser_r[0]" LOC = "T22" ; +NET "ser_r[1]" LOC = "W20" ; +NET "ser_r[2]" LOC = "W21" ; +NET "ser_r[3]" LOC = "U21" ; +NET "ser_r[4]" LOC = "V22" ; +NET "ser_r[5]" LOC = "P17" ; +NET "ser_r[6]" LOC = "R17" ; +NET "ser_r[7]" LOC = "P20" ; +NET "ser_r[8]" LOC = "R21" ; +NET "ser_r[9]" LOC = "V20" ; +NET "ser_r[10]" LOC = "W19" ; +NET "ser_r[11]" LOC = "T17" ; +NET "ser_r[12]" LOC = "T18" ; +NET "ser_r[13]" LOC = "Y22" ; +NET "ser_r[14]" LOC = "W22" ; +NET "ser_r[15]" LOC = "R20" ; +NET "ser_rklsb" LOC = "R19" ; +NET "ser_rkmsb" LOC = "T20" ; +NET "adc_a[0]" LOC = "P3" ; +NET "adc_a[1]" LOC = "N3" ; +NET "adc_a[2]" LOC = "AA1" ; +NET "adc_a[3]" LOC = "Y2" ; +NET "adc_a[4]" LOC = "C5" ; +NET "adc_a[5]" LOC = "E6" ; +NET "adc_a[6]" LOC = "C7" ; +NET "adc_a[7]" LOC = "E8" ; +NET "adc_a[8]" LOC = "F8" ; +NET "adc_a[9]" LOC = "A4" ; +NET "adc_a[10]" LOC = "B4" ; +NET "adc_a[11]" LOC = "C4" ; +NET "adc_a[12]" LOC = "D5" ; +NET "adc_a[13]" LOC = "A3" ; +NET "adc_ovf_a" LOC = "B3" ; +NET "adc_oen_a" LOC = "A6" ; +NET "adc_pdn_a" LOC = "D7" ; +NET "adc_b[0]" LOC = "J1" ; +NET "adc_b[1]" LOC = "M1" ; +NET "adc_b[2]" LOC = "P4" ; +NET "adc_b[3]" LOC = "E1" ; +NET "adc_b[4]" LOC = "D1" ; +NET "adc_b[5]" LOC = "D4" ; +NET "adc_b[6]" LOC = "D3" ; +NET "adc_b[7]" LOC = "J7" ; +NET "adc_b[8]" LOC = "J6" ; +NET "adc_b[9]" LOC = "J4" ; +NET "adc_b[10]" LOC = "J3" ; +NET "adc_b[11]" LOC = "N4" ; +NET "adc_b[12]" LOC = "M3" ; +NET "adc_b[13]" LOC = "U3" ; +NET "adc_ovf_b" LOC = "T3" ; +NET "adc_oen_b" LOC = "B6" ; +NET "adc_pdn_b" LOC = "A5" ; +NET "dac_a[0]" LOC = "N5" ; +NET "dac_a[1]" LOC = "N1" ; +NET "dac_a[2]" LOC = "K2" ; +NET "dac_a[3]" LOC = "K3" ; +NET "dac_a[4]" LOC = "K6" ; +NET "dac_a[5]" LOC = "L5" ; +NET "dac_a[6]" LOC = "H2" ; +NET "dac_a[7]" LOC = "K4" ; +NET "dac_a[8]" LOC = "K5" ; +NET "dac_a[9]" LOC = "G1" ; +NET "dac_a[10]" LOC = "H1" ; +NET "dac_a[11]" LOC = "H5" ; +NET "dac_a[12]" LOC = "H6" ; +NET "dac_a[13]" LOC = "E3" ; +NET "dac_a[14]" LOC = "E4" ; +NET "dac_a[15]" LOC = "G5" ; +NET "dac_b[0]" LOC = "G6" ; +NET "dac_b[1]" LOC = "F2" ; +NET "dac_b[2]" LOC = "F1" ; +NET "dac_b[3]" LOC = "H3" ; +NET "dac_b[4]" LOC = "H4" ; +NET "dac_b[5]" LOC = "F4" ; +NET "dac_b[6]" LOC = "F5" ; +NET "dac_b[7]" LOC = "C2" ; +NET "dac_b[8]" LOC = "C1" ; +NET "dac_b[9]" LOC = "F3" ; +NET "dac_b[10]" LOC = "G3" ; +NET "dac_b[11]" LOC = "M6" ; +NET "dac_b[12]" LOC = "N7" ; +NET "dac_b[13]" LOC = "L3" ; +NET "dac_b[14]" LOC = "M2" ; +NET "dac_b[15]" LOC = "K1" ; +NET "dac_lock" LOC = "L1" ; +NET "SCL" LOC = "B19" ; +NET "SDA" LOC = "B17" ; +NET "clk_en[0]" LOC = "AB20" ; +NET "clk_en[1]" LOC = "AA20" ; +NET "clk_sel[0]" LOC = "Y17" ; +NET "clk_sel[1]" LOC = "Y16" ; +NET "clk_func" LOC = "W13" ; +NET "clk_status" LOC = "W18" ; +NET "clk_fpga_p" LOC = "AA12" ; +NET "clk_fpga_n" LOC = "AB12" ; +NET "pps_in" LOC = "Y14" ; +NET "POR" LOC = "AB15" ; +NET "sclk" LOC = "AA14" ; +NET "sen_clk" LOC = "AB13" ; +NET "sdi" LOC = "V12" ; +NET "sdo" LOC = "U12" ; +NET "sen_dac" LOC = "W2" ; +NET "sen_tx_db" LOC = "W3" ; +NET "sen_tx_adc" LOC = "U5" ; +NET "sen_tx_dac" LOC = "U4" ; +NET "mosi_tx" LOC = "V4" ; +NET "miso_dac" LOC = "M5" ; +NET "miso_tx_db" LOC = "W1" ; +NET "miso_tx_adc" LOC = "Y1" ; +NET "sclk_tx" LOC = "V3" ; +NET "sen_rx_db" LOC = "B9" ; +NET "sclk_rx_db" LOC = "B8" ; +NET "sdo_rx_db" LOC = "A10" ; +NET "sdi_rx_db" LOC = "E12" ; +NET "sen_rx_adc" LOC = "A9" ; +NET "sclk_rx_adc" LOC = "A8" ; +NET "sdo_rx_adc" LOC = "A12" ; +NET "sdi_rx_adc" LOC = "A7" ; +NET "sen_rx_dac" LOC = "E11" ; +NET "sclk_rx_dac" LOC = "F10" ; +NET "sdi_rx_dac" LOC = "E7" ; +NET "io_tx[0]" LOC = "R3" ; +NET "io_tx[1]" LOC = "T4" ; +NET "io_tx[2]" LOC = "U2" ; +NET "io_tx[3]" LOC = "V1" ; +NET "io_tx[4]" LOC = "R5" ; +NET "io_tx[5]" LOC = "T1" ; +NET "io_tx[6]" LOC = "U1" ; +NET "io_tx[7]" LOC = "T6" ; +NET "io_tx[8]" LOC = "T5" ; +NET "io_tx[9]" LOC = "R2" ; +NET "io_tx[10]" LOC = "R1" ; +NET "io_tx[11]" LOC = "P6" ; +NET "io_tx[12]" LOC = "R6" ; +NET "io_tx[13]" LOC = "P1" ; +NET "io_tx[14]" LOC = "P2" ; +NET "io_tx[15]" LOC = "N6" ; + +NET "io_rx[0]" LOC = "G8" ; +NET "io_rx[1]" LOC = "F9" ; +NET "io_rx[2]" LOC = "C8" ; +NET "io_rx[3]" LOC = "D9" ; +NET "io_rx[4]" LOC = "C6" ; +NET "io_rx[5]" LOC = "D6" ; +NET "io_rx[6]" LOC = "C9" ; +NET "io_rx[7]" LOC = "D10" ; +NET "io_rx[8]" LOC = "B11" ; +NET "io_rx[9]" LOC = "A11" ; +NET "io_rx[10]" LOC = "C13" ; +NET "io_rx[11]" LOC = "C12" ; +NET "io_rx[12]" LOC = "F14" ; +NET "io_rx[13]" LOC = "F13" ; +NET "io_rx[14]" LOC = "D14" ; +NET "io_rx[15]" LOC = "A13" ; +NET "flash_cs" LOC = "U7" ; +NET "flash_clk" LOC = "V17" ; +NET "flash_mosi" LOC = "V13" ; +NET "flash_miso" LOC = "W17" ; + + +NET "clk_muxed" TNM_NET = "clk_muxed"; +TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + diff --git a/top/u2plus/u2plus.v b/top/u2plus/u2plus.v new file mode 100644 index 000000000..e95445867 --- /dev/null +++ b/top/u2plus/u2plus.v @@ -0,0 +1,377 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + // Misc, debug + output [4:0] leds, // LED4 is shared w/INIT_B + input [3:0] dipsw, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + input clk_to_mac, + output eth_led, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input pps_in, + input POR, + + // AD9510 SPI + output sclk, + output sen_clk, + output sdi, + input sdo, + + // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output mosi_tx, + input miso_dac, + input miso_tx_db, + input miso_tx_adc, + output sclk_tx, + + // RX side SPI + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + // FPGA-specific pins connections + wire aux_clk = PHY_CLK; + + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge aux_clk) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_muxed), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + //.uart_rx_i (uart_rx_i), + .uart_rx_i (), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2plus |