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+
+# My stuff
+-y .
+-y ../top/u2_core
+-y ../control_lib
+-y ../serdes
+-y ../sdr_lib
+-y ../timing
+-y ../coregen
+
+# Models
+-y ../models
+-y ../models/CY7C1356C
+
+# Open Cores
+-y ../opencores/8b10b
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/wb_conbus/rtl/verilog
++incdir+../opencores/wb_conbus/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+-y ../opencores/aemb/rtl/verilog
+-y ../opencores/simple_pic/rtl
+
+# Ethernet
++incdir+../eth/rtl/verilog
+-y ../eth/rtl/verilog
+-y ../eth/rtl/verilog/MAC_tx
+-y ../eth/rtl/verilog/MAC_rx
+-y ../eth/rtl/verilog/miim
+-y ../eth/rtl/verilog/TECH
+-y ../eth/rtl/verilog/TECH/xilinx
+-y ../eth/rtl/verilog/RMON
+-y ../eth
+-y ../eth/bench/verilog
+
+# Ethernet Models
+-y ../eth/bench/verilog