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-rw-r--r--simple_gemac/simple_gemac.v5
-rw-r--r--simple_gemac/simple_gemac_tb.v4
2 files changed, 4 insertions, 5 deletions
diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v
index 84a997666..adcc2d2fb 100644
--- a/simple_gemac/simple_gemac.v
+++ b/simple_gemac/simple_gemac.v
@@ -6,7 +6,7 @@ module simple_gemac
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
// Flow Control Interface
- input pause_req, input [15:0] pause_time,
+ input pause_req, input [15:0] pause_time, input pause_en,
// RX Client Interface
output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack,
@@ -16,7 +16,6 @@ module simple_gemac
);
localparam SGE_IFG = 8'd12; // 12 should be the absolute minimum
- localparam SGE_RESPECT_FLOW_CTRL = 1'b1; // stop sending if other side requests
wire rst_rxclk, rst_txclk;
oneshot_2clk tx_rst_1shot (.clk_in(tx_clk),.in(reset),.clk_out(tx_clk),.out(rst_txclk)); // FIXME clocks
@@ -51,7 +50,7 @@ module simple_gemac
flow_ctrl_tx flow_ctrl_tx
(.rst(rst_txclk), .tx_clk(tx_clk),
- .tx_pause_en(SGE_RESPECT_FLOW_CTRL),
+ .tx_pause_en(pause_en),
.pause_quanta(pause_quanta_rcvd), // 16 bit value
.pause_quanta_val(pause_rcvd),
.pause_apply(pause_apply),
diff --git a/simple_gemac/simple_gemac_tb.v b/simple_gemac/simple_gemac_tb.v
index 8d5416f94..cd2db01b5 100644
--- a/simple_gemac/simple_gemac_tb.v
+++ b/simple_gemac/simple_gemac_tb.v
@@ -36,7 +36,7 @@ module simple_gemac_tb;
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
- .pause_req(pause_req), .pause_time(pause_time),
+ .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
.rx_clk(rx_clk), .rx_data(rx_data),
.rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
.tx_clk(tx_clk), .tx_data(tx_data),
@@ -178,7 +178,7 @@ module simple_gemac_tb;
end
// Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
- // Still need to test: ?
+ // Still need to test: CRC errors on Pause Frames
always @(posedge clk)
if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)