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-rw-r--r--simple_gemac/simple_gemac_rx.v2
-rw-r--r--simple_gemac/simple_gemac_wrapper.v2
2 files changed, 2 insertions, 2 deletions
diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v
index c50791ff0..bad43a607 100644
--- a/simple_gemac/simple_gemac_rx.v
+++ b/simple_gemac/simple_gemac_rx.v
@@ -1,7 +1,7 @@
module simple_gemac_rx
- (input clk125, input reset,
+ (input reset,
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
input [47:0] ucast_addr, input [47:0] mcast_addr,
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index 7511f3fb9..71ad0cf0f 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -110,7 +110,7 @@ module simple_gemac_wrapper
wire [35:0] tx_f36_data_int1;
wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
- fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
+ fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
(.wclk(sys_clk), .datain(tx_f36_data),
.src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
.rclk(tx_clk), .dataout(tx_f36_data_int1),