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-rw-r--r--simple_gemac/.gitignore3
-rw-r--r--simple_gemac/delay_line.v2
-rw-r--r--simple_gemac/eth_tasks_f36.v92
-rw-r--r--simple_gemac/flow_ctrl_rx.v106
-rw-r--r--simple_gemac/ll8_shortfifo.v13
-rw-r--r--simple_gemac/rxmac_to_ll8.v14
-rw-r--r--simple_gemac/simple_gemac.v9
-rw-r--r--simple_gemac/simple_gemac_rx.v50
-rw-r--r--simple_gemac/simple_gemac_tx.v16
-rw-r--r--simple_gemac/simple_gemac_wb.v35
-rwxr-xr-xsimple_gemac/simple_gemac_wrapper.build1
-rw-r--r--simple_gemac/simple_gemac_wrapper.v159
-rw-r--r--simple_gemac/simple_gemac_wrapper_f36_tb.v243
-rw-r--r--simple_gemac/simple_gemac_wrapper_tb.v140
14 files changed, 640 insertions, 243 deletions
diff --git a/simple_gemac/.gitignore b/simple_gemac/.gitignore
index 61e120cff..17f35e962 100644
--- a/simple_gemac/.gitignore
+++ b/simple_gemac/.gitignore
@@ -1,3 +1,4 @@
/a.out
-/*~
/*.vcd
+simple_gemac_wrapper_tb
+
diff --git a/simple_gemac/delay_line.v b/simple_gemac/delay_line.v
index 3d76c4928..d371bb9c5 100644
--- a/simple_gemac/delay_line.v
+++ b/simple_gemac/delay_line.v
@@ -7,7 +7,7 @@ module delay_line
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout);
- integer i;
+ genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_delay
diff --git a/simple_gemac/eth_tasks_f36.v b/simple_gemac/eth_tasks_f36.v
new file mode 100644
index 000000000..efd72778b
--- /dev/null
+++ b/simple_gemac/eth_tasks_f36.v
@@ -0,0 +1,92 @@
+
+
+task SendFlowCtrl;
+ input [15:0] fc_len;
+ begin
+ $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+ pause_time <= fc_len;
+ @(posedge eth_clk);
+ pause_req <= 1;
+ @(posedge eth_clk);
+ pause_req <= 0;
+ $display("Sent Flow Control");
+ end
+endtask // SendFlowCtrl
+
+task SendPacket_to_fifo36;
+ input [31:0] data_start;
+ input [15:0] data_len;
+ reg [15:0] count;
+ begin
+ $display("Sending Packet Len=%d, %d", data_len, $time);
+ count <= 2;
+ tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
+ tx_f36_src_rdy <= 1;
+ #1;
+ while(count < data_len)
+ begin
+ while(~tx_f36_dst_rdy)
+ @(posedge sys_clk);
+ @(posedge sys_clk);
+ tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
+ count = count + 4;
+ tx_f36_data[32] <= 0;
+ end
+ tx_f36_data[33] <= 1;
+ while(~tx_f36_dst_rdy)
+ @(posedge sys_clk);
+ @(posedge sys_clk);
+ tx_f36_src_rdy <= 0;
+ end
+endtask // SendPacket_to_fifo36
+
+/*
+task Waiter;
+ input [31:0] wait_length;
+ begin
+ tx_ll_src_rdy2 <= 0;
+ repeat(wait_length)
+ @(posedge clk);
+ tx_ll_src_rdy2 <= 1;
+ end
+endtask // Waiter
+*/
+
+/*
+task SendPacketFromFile_f36;
+ input [31:0] data_len;
+ input [31:0] wait_length;
+ input [31:0] wait_time;
+
+ integer count;
+ begin
+ $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+ $readmemh("test_packet.mem",pkt_rom );
+
+ while(~tx_f36_dst_rdy)
+ @(posedge clk);
+ tx_f36_data <= pkt_rom[0];
+ tx_f36_src_rdy <= 1;
+ tx_f36_eof <= 0;
+ @(posedge clk);
+
+ for(i=1;i<data_len-1;i=i+1)
+ begin
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ tx_ll_data2 <= pkt_rom[i];
+ tx_ll_sof2 <= 0;
+ @(posedge clk);
+// if(i==wait_time)
+// Waiter(wait_length);
+ end
+
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ tx_ll_eof2 <= 1;
+ tx_ll_data2 <= pkt_rom[data_len-1];
+ @(posedge clk);
+ tx_ll_src_rdy2 <= 0;
+ end
+endtask
+*/
diff --git a/simple_gemac/flow_ctrl_rx.v b/simple_gemac/flow_ctrl_rx.v
index 7ded9e08b..d09bf377f 100644
--- a/simple_gemac/flow_ctrl_rx.v
+++ b/simple_gemac/flow_ctrl_rx.v
@@ -2,84 +2,60 @@
// RX side of flow control -- when we are running out of RX space, send a PAUSE
module flow_ctrl_rx
- (input rst,
- //host processor
- input pause_frame_send_en,
- input [15:0] pause_quanta_set,
- input [15:0] fc_hwmark,
- input [15:0] fc_lwmark,
- // From MAC_rx_ctrl
- input rx_clk,
- input [15:0] rx_fifo_space,
- // MAC_tx_ctrl
- input tx_clk,
- output reg xoff_gen,
- output reg xon_gen,
- input xoff_gen_complete,
- input xon_gen_complete
+ (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh,
+ input rx_clk, input rx_reset, input [15:0] rx_fifo_space,
+ input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req
);
// ******************************************************************************
// Force our TX to send a PAUSE frame because our RX is nearly full
// ******************************************************************************
- reg xon_int, xoff_int;
+ // RX Clock Domain
+ reg xon, xoff;
reg [21:0] countdown;
-
- always @(posedge rx_clk or posedge rst)
- if(rst)
- begin
- xon_int <= 0;
- xoff_int <= 0;
- end
- else
- begin
- xon_int <= 0;
- xoff_int <= 0;
- if(pause_frame_send_en)
- if(countdown == 0)
- if(rx_fifo_space < fc_lwmark)
- xoff_int <= 1;
- else
- ;
- else
- if(rx_fifo_space > fc_hwmark)
- xon_int <= 1;
- end // else: !if(rst)
-
- reg xoff_int_d1, xon_int_d1;
- always @(posedge rx_clk)
- xon_int_d1 <= xon_int;
- always @(posedge rx_clk)
- xoff_int_d1 <= xoff_int;
+ wire [15:0] pause_low_thresh = pause_thresh;
+ wire [15:0] pause_hi_thresh = 16'hFFFF;
+ wire [21:0] pq_reduced = {pause_time,6'd0} - 1700;
- always @ (posedge tx_clk or posedge rst)
- if (rst)
- xoff_gen <=0;
- else if (xoff_gen_complete)
- xoff_gen <=0;
- else if (xoff_int | xoff_int_d1)
- xoff_gen <=1;
+ always @(posedge rx_clk)
+ if(rx_reset)
+ xoff <= 0;
+ else
+ xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh));
- always @ (posedge tx_clk or posedge rst)
- if (rst)
- xon_gen <=0;
- else if (xon_gen_complete)
- xon_gen <=0;
- else if (xon_int | xon_int_d1)
- xon_gen <=1;
-
- wire [15:0] pq_reduced = pause_quanta_set - 2;
+ always @(posedge rx_clk)
+ if(rx_reset)
+ xon <= 0;
+ else
+ xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh));
- always @(posedge tx_clk or posedge rst)
- if(rst)
+ always @(posedge rx_clk)
+ if(rx_reset)
countdown <= 0;
- else if(xoff_gen)
- countdown <= {pq_reduced,6'd0};
- else if(xon_gen)
+ else if(xoff)
+ countdown <= pq_reduced;
+ else if(xon)
countdown <= 0;
else if(countdown != 0)
countdown <= countdown - 1;
+
+ // Cross clock domains
+ wire xon_tx, xoff_tx;
+ oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));
+ oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));
+
+ always @(posedge tx_clk)
+ if(xoff_tx)
+ pause_time_req <= pause_time;
+ else if(xon_tx)
+ pause_time_req <= 0;
+
+ always @(posedge tx_clk)
+ if(tx_reset)
+ pause_req <= 0;
+ else
+ pause_req <= xon_tx | xoff_tx;
-endmodule // flow_ctrl
+endmodule // flow_ctrl_rx
diff --git a/simple_gemac/ll8_shortfifo.v b/simple_gemac/ll8_shortfifo.v
index 39ada9a4f..e69de29bb 100644
--- a/simple_gemac/ll8_shortfifo.v
+++ b/simple_gemac/ll8_shortfifo.v
@@ -1,13 +0,0 @@
-
-
-module ll8_shortfifo
- (input clk, input reset, input clear,
- input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
- output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
-
- fifo_short #(.WIDTH(11)) fifo_short
- (.clk(clk), .reset(reset), .clear(clear),
- .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
- .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
-
-endmodule // ll8_shortfifo
diff --git a/simple_gemac/rxmac_to_ll8.v b/simple_gemac/rxmac_to_ll8.v
index d4015716e..5ec233d95 100644
--- a/simple_gemac/rxmac_to_ll8.v
+++ b/simple_gemac/rxmac_to_ll8.v
@@ -6,6 +6,13 @@ module rxmac_to_ll8
reg [2:0] xfer_state;
+ localparam XFER_IDLE = 0;
+ localparam XFER_ACTIVE = 1;
+ localparam XFER_ERROR = 2;
+ localparam XFER_ERROR2 = 3;
+ localparam XFER_OVERRUN = 4;
+ localparam XFER_OVERRUN2 = 5;
+
assign ll_data = rx_data;
assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
| (xfer_state == XFER_ERROR)
@@ -14,13 +21,6 @@ module rxmac_to_ll8
assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN);
- localparam XFER_IDLE = 0;
- localparam XFER_ACTIVE = 1;
- localparam XFER_ERROR = 2;
- localparam XFER_ERROR2 = 3;
- localparam XFER_OVERRUN = 4;
- localparam XFER_OVERRUN2 = 5;
-
always @(posedge clk)
if(reset | clear)
xfer_state <= XFER_IDLE;
diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v
index 5ec2fa2ba..e7f327358 100644
--- a/simple_gemac/simple_gemac.v
+++ b/simple_gemac/simple_gemac.v
@@ -6,7 +6,7 @@ module simple_gemac
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
// Flow Control Interface
- input pause_req, input [15:0] pause_time, input pause_en,
+ input pause_req, input [15:0] pause_time_req, input pause_respect_en,
// Settings
input [47:0] ucast_addr, input [47:0] mcast_addr,
@@ -26,14 +26,15 @@ module simple_gemac
reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
wire [15:0] pause_quanta_rcvd;
-
+ wire pause_rcvd, pause_apply, paused;
+
simple_gemac_tx simple_gemac_tx
(.clk125(clk125),.reset(rst_txclk),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
.ifg(SGE_IFG), .mac_addr(ucast_addr),
- .pause_req(pause_req), .pause_time(pause_time), // We request flow control
+ .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control
.pause_apply(pause_apply), .paused(paused) // We respect flow control
);
@@ -50,7 +51,7 @@ module simple_gemac
flow_ctrl_tx flow_ctrl_tx
(.rst(rst_txclk), .tx_clk(tx_clk),
- .tx_pause_en(pause_en),
+ .tx_pause_en(pause_respect_en),
.pause_quanta(pause_quanta_rcvd), // 16 bit value
.pause_quanta_val(pause_rcvd),
.pause_apply(pause_apply),
diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v
index 7daa9adad..45ddd6dfa 100644
--- a/simple_gemac/simple_gemac_rx.v
+++ b/simple_gemac/simple_gemac_rx.v
@@ -1,14 +1,31 @@
module simple_gemac_rx
- (input clk125, input reset,
+ (input reset,
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
input [47:0] ucast_addr, input [47:0] mcast_addr,
input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
output reg [15:0] pause_quanta_rcvd, output pause_rcvd );
- reg [7:0] rxd_d1;
+ localparam RX_IDLE = 0;
+ localparam RX_PREAMBLE = 1;
+ localparam RX_FRAME = 2;
+ localparam RX_GOODFRAME = 3;
+ localparam RX_DO_PAUSE = 4;
+ localparam RX_ERROR = 5;
+ localparam RX_DROP = 6;
+
+ localparam RX_PAUSE = 16;
+ localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
+ localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
+ localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
+ localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
+ localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
+ localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
+ localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
+
+ reg [7:0] rxd_d1;
reg rx_dv_d1, rx_er_d1;
assign rx_clk = GMII_RX_CLK;
@@ -19,13 +36,18 @@ module simple_gemac_rx
rxd_d1 <= GMII_RXD;
end
+ reg [7:0] rx_state;
wire [7:0] rxd_del;
wire rx_dv_del, rx_er_del;
reg go_filt;
+ wire match_crc;
+ wire clear_crc = rx_state == RX_IDLE;
+ wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
+
localparam DELAY = 6;
delay_line #(.WIDTH(10)) rx_delay
- (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del}));
+ (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
always @(posedge rx_clk)
if(reset)
@@ -37,7 +59,6 @@ module simple_gemac_rx
wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
(pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
- reg [7:0] rx_state;
assign rx_data = rxd_del;
assign rx_error = (rx_state == RX_ERROR);
@@ -58,24 +79,6 @@ module simple_gemac_rx
address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(48'h0180_c200_0001), .match(is_pause), .done());
- localparam RX_IDLE = 0;
- localparam RX_PREAMBLE = 1;
- localparam RX_FRAME = 2;
- localparam RX_GOODFRAME = 3;
- localparam RX_DO_PAUSE = 4;
- localparam RX_ERROR = 5;
- localparam RX_DROP = 6;
-
- localparam RX_PAUSE = 16;
- localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
- localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
- localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
- localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
- localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
- localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
- localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
-
-
always @(posedge rx_clk)
go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
@@ -155,9 +158,6 @@ module simple_gemac_rx
endcase // case (rx_state)
assign pause_rcvd = (rx_state == RX_DO_PAUSE);
- wire match_crc;
- wire clear_crc = rx_state == RX_IDLE;
- wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
.data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
diff --git a/simple_gemac/simple_gemac_tx.v b/simple_gemac/simple_gemac_tx.v
index 690fd5c37..dd870d04d 100644
--- a/simple_gemac/simple_gemac_tx.v
+++ b/simple_gemac/simple_gemac_tx.v
@@ -23,14 +23,6 @@ module simple_gemac_tx
wire [31:0] crc_out;
- localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC
- localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle?
- always @(posedge tx_clk)
- if(reset |(tx_state == TX_IDLE))
- frame_len_ctr <= 0;
- else
- frame_len_ctr <= frame_len_ctr + 1;
-
localparam TX_IDLE = 0;
localparam TX_PREAMBLE = 1;
localparam TX_SOF_DEL = TX_PREAMBLE + 7;
@@ -48,6 +40,14 @@ module simple_gemac_tx
localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
localparam TX_PAUSE_END = TX_PAUSE_SOF + 18;
+ localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC
+ localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle?
+ always @(posedge tx_clk)
+ if(reset |(tx_state == TX_IDLE))
+ frame_len_ctr <= 0;
+ else
+ frame_len_ctr <= frame_len_ctr + 1;
+
reg send_pause;
reg [15:0] pause_time_held;
diff --git a/simple_gemac/simple_gemac_wb.v b/simple_gemac/simple_gemac_wb.v
index ca7d4a3fc..6df277e3e 100644
--- a/simple_gemac/simple_gemac_wb.v
+++ b/simple_gemac/simple_gemac_wb.v
@@ -24,7 +24,9 @@ module simple_gemac_wb
inout mdio, output mdc,
output [47:0] ucast_addr, output [47:0] mcast_addr,
output pass_ucast, output pass_mcast, output pass_bcast,
- output pass_pause, output pass_all, output pause_en );
+ output pass_pause, output pass_all,
+ output pause_respect_en, output pause_request_en,
+ output [15:0] pause_time, output [15:0] pause_thresh );
wire acc = wb_cyc & wb_stb;
wire wr_acc = wb_cyc & wb_stb & wb_we;
@@ -36,10 +38,10 @@ module simple_gemac_wb
else
wb_ack <= acc & ~wb_ack;
- wire [5:0] misc_settings;
- assign {pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en} = misc_settings;
+ wire [6:0] misc_settings;
+ assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
- wb_reg #(.ADDR(0),.DEFAULT(6'b111001))
+ wb_reg #(.ADDR(0),.DEFAULT(7'b0111001))
wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(misc_settings) );
wb_reg #(.ADDR(1),.DEFAULT(0))
@@ -79,20 +81,23 @@ module simple_gemac_wb
wire [2:0] MIISTATUS;
wb_reg #(.ADDR(5),.DEFAULT(0))
- wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
+ wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+ .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
wb_reg #(.ADDR(6),.DEFAULT(0))
- wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
+ wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+ .dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
wb_reg #(.ADDR(7),.DEFAULT(0))
- wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o(CtrlData) );
+ wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+ .dat_i(wb_dat_i), .dat_o(CtrlData) );
// MIICOMMAND register - needs special treatment because of auto-resetting bits
always @ (posedge wb_clk)
if (wb_rst)
MIICOMMAND <= 0;
else
- if (wr_acc & (wb_adr == 8'd8))
+ if (wr_acc & (wb_adr[7:2] == 6'd8))
MIICOMMAND <= wb_dat_i;
else
begin
@@ -128,8 +133,16 @@ module simple_gemac_wb
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
+ wb_reg #(.ADDR(11),.DEFAULT(0))
+ wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+ .dat_i(wb_dat_i), .dat_o(pause_time) );
+
+ wb_reg #(.ADDR(12),.DEFAULT(0))
+ wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+ .dat_i(wb_dat_i), .dat_o(pause_thresh) );
+
always @(posedge wb_clk)
- case(wb_adr)
+ case(wb_adr[7:2])
0 : wb_dat_o <= misc_settings;
1 : wb_dat_o <= ucast_addr[47:32];
2 : wb_dat_o <= ucast_addr[31:0];
@@ -141,6 +154,8 @@ module simple_gemac_wb
8 : wb_dat_o <= MIICOMMAND;
9 : wb_dat_o <= MIISTATUS;
10: wb_dat_o <= MIIRX_DATA;
- endcase // case (wb_adr)
+ 11: wb_dat_o <= pause_time;
+ 12: wb_dat_o <= pause_thresh;
+ endcase // case (wb_adr[7:2])
endmodule // simple_gemac_wb
diff --git a/simple_gemac/simple_gemac_wrapper.build b/simple_gemac/simple_gemac_wrapper.build
new file mode 100755
index 000000000..30f65ab17
--- /dev/null
+++ b/simple_gemac/simple_gemac_wrapper.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index cd586ae5d..efcf89276 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -1,46 +1,48 @@
module simple_gemac_wrapper
- (input clk125, input reset,
- // GMII
- output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
- input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
-
- // Flow Control Interface
- input pause_req, input [15:0] pause_time,
-
- // RX Client Interface
- output rx_clk, output [7:0] rx_ll_data, output rx_ll_sof, output rx_ll_eof,
- output rx_ll_error, output rx_ll_src_rdy, input rx_ll_dst_rdy,
-
- // TX Client Interface
- output tx_clk, input [7:0] tx_ll_data, input tx_ll_sof, input tx_ll_eof,
- input tx_ll_src_rdy, output tx_ll_dst_rdy,
-
- // Wishbone Interface
- input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
- input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+ #(parameter RXFIFOSIZE=9,
+ parameter TXFIFOSIZE=6)
+ (input clk125, input reset,
+ // GMII
+ output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+ input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+
+ // Client FIFO Interfaces
+ input sys_clk,
+ output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
+ input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
+
+ // Wishbone Interface
+ input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
+ input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+
+ // MIIM
+ inout mdio, output mdc,
+ output [31:0] debug);
+
+ wire clear = 0;
+ wire [7:0] rx_data, tx_data;
+ wire tx_clk, tx_valid, tx_error, tx_ack;
+ wire rx_clk, rx_valid, rx_error, rx_ack;
- // MIIM
- inout mdio, output mdc );
+ wire [47:0] ucast_addr, mcast_addr;
+ wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+ wire pause_req;
+ wire pause_request_en, pause_respect_en;
+ wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space;
- wire [7:0] rx_data, tx_data;
- wire tx_clk, tx_valid, tx_error, tx_ack;
- wire rx_clk, rx_valid, rx_error, rx_ack;
-
- wire [47:0] ucast_addr, mcast_addr;
- wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en;
-
- wire rst_rxclk, rst_txclk;
+ wire tx_reset, rx_reset;
reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
-
+
simple_gemac simple_gemac
(.clk125(clk125), .reset(reset),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
- .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+ .pause_req(pause_req), .pause_time_req(pause_time_req),
+ .pause_respect_en(pause_respect_en),
.ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
.pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
.pass_pause(pass_pause), .pass_all(pass_all),
@@ -57,18 +59,107 @@ module simple_gemac_wrapper
.mdio(mdio), .mdc(mdc),
.ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
.pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
- .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) );
+ .pass_pause(pass_pause), .pass_all(pass_all),
+ .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
+ .pause_time(pause_time), .pause_thresh(pause_thresh) );
+ // RX FIFO Chain
+ wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+
+ wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+ wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+
+ wire [7:0] rx_ll_data, rx_ll_data2;
+
+ wire [35:0] rx_f36_data_int1;
+ wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+
rxmac_to_ll8 rx_adapt
(.clk(rx_clk), .reset(rx_reset), .clear(0),
.rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
- .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
+ .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof
.ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+ ll8_shortfifo rx_sfifo
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+ .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+ .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+ .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+ assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n;
+ assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+ assign rx_ll_sof2_n = ~rx_ll_sof2;
+ assign rx_ll_eof2_n = ~rx_ll_eof2;
+
+ ll8_to_fifo36 ll8_to_fifo36
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+ .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+ .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+
+ fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+ (.wclk(rx_clk), .datain(rx_f36_data_int1),
+ .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
+ .rclk(sys_clk), .dataout(rx_f36_data),
+ .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
+
+ // TX FIFO Chain
+ wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+ wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+ wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
+ wire [7:0] tx_ll_data, tx_ll_data2;
+ wire [35:0] tx_f36_data_int1;
+ wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
+
+ fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
+ (.wclk(sys_clk), .datain(tx_f36_data),
+ .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
+ .rclk(tx_clk), .dataout(tx_f36_data_int1),
+ .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
+
+ fifo36_to_ll8 fifo36_to_ll8
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+ .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
+ .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+ .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+
+ assign tx_ll_sof2 = ~tx_ll_sof2_n;
+ assign tx_ll_eof2 = ~tx_ll_eof2_n;
+ assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n;
+ assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2;
+
+ ll8_shortfifo tx_sfifo
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+ .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+ .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+ .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+ .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
ll8_to_txmac ll8_to_txmac
- (.clk(tx_clk), .reset(tx_reset), .clear(0),
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
.ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+ flow_ctrl_rx flow_ctrl_rx
+ (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
+ .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
+ .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
+
+ wire [31:0] debug_tx, debug_rx;
+
+ assign debug_tx = { { tx_ll_data },
+ { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy,
+ tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+ { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
+ { tx_data} };
+ assign debug_rx = { { rx_ll_data },
+ { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy,
+ rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+ { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+ { rx_data} };
+
+ assign debug = debug_rx;
+
endmodule // simple_gemac_wrapper
diff --git a/simple_gemac/simple_gemac_wrapper_f36_tb.v b/simple_gemac/simple_gemac_wrapper_f36_tb.v
new file mode 100644
index 000000000..804fa8748
--- /dev/null
+++ b/simple_gemac/simple_gemac_wrapper_f36_tb.v
@@ -0,0 +1,243 @@
+
+
+module simple_gemac_wrapper_f36_tb;
+`include "eth_tasks_f36.v"
+
+ reg clk = 0;
+ reg reset = 1;
+
+ initial #1000 reset = 0;
+ always #50 clk = ~clk;
+
+ reg wb_clk = 0;
+ wire wb_rst = reset;
+ always #173 wb_clk = ~wb_clk;
+
+ wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+ wire [7:0] GMII_RXD, GMII_TXD;
+
+ wire rx_valid, rx_error, rx_ack;
+ wire tx_ack, tx_valid, tx_error;
+
+ wire [7:0] rx_data, tx_data;
+
+ reg [15:0] pause_time;
+ reg pause_req = 0;
+
+ wire GMII_RX_CLK = GMII_GTX_CLK;
+
+ reg [7:0] FORCE_DAT_ERR = 0;
+ reg FORCE_ERR = 0;
+
+ // Loopback
+ assign GMII_RX_DV = GMII_TX_EN;
+ assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR;
+ assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+ wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+ wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+ wire rx_ll_dst_rdy2;
+ wire [7:0] rx_ll_data, rx_ll_data2;
+ wire rx_ll_error, rx_ll_error2;
+
+ wire [31:0] wb_dat_o;
+ reg [31:0] wb_dat_i;
+ reg [7:0] wb_adr;
+ reg wb_stb=0, wb_cyc=0, wb_we=0;
+ wire wb_ack;
+
+ reg [35:0] tx_f36_dat;
+ reg tx_f36_src_rdy;
+ wire tx_f36_dst_rdy;
+
+ wire [35:0] rx_f36_dat;
+ wire rx_f36_src_rdy;
+ reg rx_f36_dst_rdy = 1;
+
+ simple_gemac_wrapper simple_gemac_wrapper
+ (.clk125(clk), .reset(reset),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .pause_req(pause_req), .pause_time(pause_time),
+ .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),
+ .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy),
+ .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),
+ .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy),
+ .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),
+ .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+ .mdio(mdio), .mdc(mdc) );
+
+ wire rx_ll_dst_rdy2_n;
+ assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n;
+
+ ll8_shortfifo rx_sfifo
+ (.clk(clk), .reset(reset), .clear(0),
+ .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+ .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+ .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+ .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+ ll8_to_fifo36 ll8_to_fifo36
+ (.clk(clk), .reset(reset), .clear(0),
+ .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2),
+ .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+ .f36_data(rx_f36_dat), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy));
+
+ wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+ wire tx_ll_sof2_n, tx_ll_eof2_n;
+ wire tx_ll_src_rdy2_n, tx_ll_dst_rdy2;
+ wire [7:0] tx_ll_data, tx_ll_data2;
+ wire tx_ll_error;
+ wire tx_ll_error2 = 0;
+
+ fifo36_to_ll8 fifo36_to_ll8
+ (.clk(clk), .reset(reset), .clear(clear),
+ .f36_data(tx_f36_dat), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
+ .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+ .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2));
+
+ ll8_shortfifo tx_sfifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(tx_ll_data2), .sof_i(~tx_ll_sof2_n), .eof_i(~tx_ll_eof2_n),
+ .error_i(tx_ll_error2), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2),
+ .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+ .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+
+ initial $dumpfile("simple_gemac_wrapper_f36_tb.vcd");
+ initial $dumpvars(0,simple_gemac_wrapper_f36_tb);
+
+ integer i;
+ reg [7:0] pkt_rom[0:65535];
+ reg [1023:0] ROMFile;
+
+ initial
+ for (i=0;i<65536;i=i+1)
+ pkt_rom[i] <= 8'h0;
+
+ initial
+ begin
+ @(negedge reset);
+ repeat (10)
+ @(posedge clk);
+ WishboneWR(0,6'b111001);
+ WishboneWR(4,16'hF1F2);
+ WishboneWR(8,32'hF3F4_F5F6);
+ WishboneWR(12,16'h0000);
+ WishboneWR(16,32'h0000_0000);
+
+ @(posedge clk);
+ SendFlowCtrl(16'h0007); // Send flow control
+ @(posedge clk);
+ #30000;
+ @(posedge clk);
+ SendFlowCtrl(16'h0009); // Increase flow control before it expires
+ #10000;
+ @(posedge clk);
+ SendFlowCtrl(16'h0000); // Cancel flow control before it expires
+ @(posedge clk);
+
+ SendPacket_to_fifo36(8'hAA,10); // This packet gets dropped by the filters
+ repeat (10)
+ @(posedge clk);
+
+ SendPacketFromFile_fifo36(60,0,0); // The rest are valid packets
+ repeat (10)
+ @(posedge clk);
+
+ SendPacketFromFile_fifo36(61,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(62,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(63,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(64,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(59,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(58,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(100,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(200,150,30); // waiting 14 empties the fifo, 15 underruns
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_fifo36(100,0,30);
+ #10000 $finish;
+ end
+/*
+ // Force a CRC error
+ initial
+ begin
+ #90000;
+ @(posedge clk);
+ FORCE_DAT_ERR <= 8'h10;
+ @(posedge clk);
+ FORCE_DAT_ERR <= 8'h00;
+ end
+
+ // Force an RX_ER error (i.e. link loss)
+ initial
+ begin
+ #116000;
+ @(posedge clk);
+ FORCE_ERR <= 1;
+ @(posedge clk);
+ FORCE_ERR <= 0;
+ end
+
+ // Cause receive fifo to fill, causing an RX overrun
+ initial
+ begin
+ #126000;
+ @(posedge clk);
+ rx_f36_dst_rdy <= 0;
+ repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows
+ @(posedge clk);
+ rx_f36_dst_rdy <= 1;
+ end
+ */
+ // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+ // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+ task WishboneWR;
+ input [7:0] adr;
+ input [31:0] value;
+ begin
+ wb_adr <= adr;
+ wb_dat_i <= value;
+ wb_stb <= 1;
+ wb_cyc <= 1;
+ wb_we <= 1;
+ while (~wb_ack)
+ @(posedge wb_clk);
+ @(posedge wb_clk);
+ wb_stb <= 0;
+ wb_cyc <= 0;
+ wb_we <= 0;
+ end
+ endtask // WishboneWR
+
+ always @(posedge clk)
+ if(rx_f36_src_rdy & rx_f36_dst_rdy)
+ begin
+ if(rx_f36_dat[32] & ~rx_f36_dat[33])
+ $display("RX-PKT-START %d",$time);
+ $display("RX-PKT SOF %d EOF %d ERR %d OCC %d DAT %x",rx_f36_dat[32],rx_f36_dat[33],
+ &rx_f36_dat[33:32],rx_f36_dat[35:34],rx_f36_dat[31:0]);
+ if(rx_f36_dat[33] & ~rx_f36_dat[32])
+ $display("RX-PKT-END %d",$time);
+ if(rx_f36_dat[33] & rx_f36_dat[32])
+ $display("RX-PKT-ERROR %d",$time);
+ end
+
+endmodule // simple_gemac_wrapper_tb
diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/simple_gemac/simple_gemac_wrapper_tb.v
index b51afa5bb..26a471a49 100644
--- a/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/simple_gemac/simple_gemac_wrapper_tb.v
@@ -1,18 +1,21 @@
module simple_gemac_wrapper_tb;
-`include "eth_tasks.v"
+`include "eth_tasks_f36.v"
- reg clk = 0;
reg reset = 1;
-
initial #1000 reset = 0;
- always #50 clk = ~clk;
+ wire wb_rst = reset;
+
+ reg eth_clk = 0;
+ always #50 eth_clk = ~eth_clk;
reg wb_clk = 0;
- wire wb_rst = reset;
always #173 wb_clk = ~wb_clk;
-
+
+ reg sys_clk = 0;
+ always #77 sys_clk = ~ sys_clk;
+
wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
wire [7:0] GMII_RXD, GMII_TXD;
@@ -35,55 +38,35 @@ module simple_gemac_wrapper_tb;
assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
- wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
- wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
- reg rx_ll_dst_rdy2 = 1;
- wire [7:0] rx_ll_data, rx_ll_data2;
- wire rx_ll_error, rx_ll_error2;
-
wire [31:0] wb_dat_o;
reg [31:0] wb_dat_i;
reg [7:0] wb_adr;
reg wb_stb=0, wb_cyc=0, wb_we=0;
wire wb_ack;
+
+ reg [35:0] tx_f36_data=0;
+ reg tx_f36_src_rdy = 0;
+ wire tx_f36_dst_rdy;
+ wire rx_f36_data;
+ wire rx_f36_src_rdy;
+ wire rx_f36_dst_rdy = 1;
simple_gemac_wrapper simple_gemac_wrapper
- (.clk125(clk), .reset(reset),
+ (.clk125(eth_clk), .reset(reset),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.pause_req(pause_req), .pause_time(pause_time),
- .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),
- .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy),
- .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),
- .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy),
- .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),
- .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
- .mdio(mdio), .mdc(mdc) );
-
- ll8_shortfifo rx_sfifo
- (.clk(clk), .reset(reset), .clear(0),
- .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
- .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
- .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
- .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
-
- wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
- reg tx_ll_sof2=0, tx_ll_eof2=0;
- reg tx_ll_src_rdy2 = 0;
- wire tx_ll_dst_rdy2;
- wire [7:0] tx_ll_data;
- reg [7:0] tx_ll_data2 = 0;
- wire tx_ll_error;
- wire tx_ll_error2 = 0;
-
- ll8_shortfifo tx_sfifo
- (.clk(clk), .reset(reset), .clear(clear),
- .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
- .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
- .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
- .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+
+ .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+ .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
+
+ .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+ .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+ .mdio(), .mdc(),
+ .debug() );
initial $dumpfile("simple_gemac_wrapper_tb.vcd");
initial $dumpvars(0,simple_gemac_wrapper_tb);
@@ -100,67 +83,74 @@ module simple_gemac_wrapper_tb;
begin
@(negedge reset);
repeat (10)
- @(posedge clk);
- WishboneWR(0,6'b111001);
- WishboneWR(4,16'hF1F2);
- WishboneWR(8,32'hF3F4_F5F6);
+ @(posedge wb_clk);
+ WishboneWR(0,6'b111101);
+ WishboneWR(4,16'hA0B0);
+ WishboneWR(8,32'hC0D0_A1B1);
WishboneWR(12,16'h0000);
WishboneWR(16,32'h0000_0000);
- @(posedge clk);
+ @(posedge eth_clk);
SendFlowCtrl(16'h0007); // Send flow control
- @(posedge clk);
+ @(posedge eth_clk);
#30000;
- @(posedge clk);
- SendFlowCtrl(16'h0009); // Increas flow control before it expires
+ @(posedge eth_clk);
+ SendFlowCtrl(16'h0009); // Increase flow control before it expires
#10000;
- @(posedge clk);
+ @(posedge eth_clk);
SendFlowCtrl(16'h0000); // Cancel flow control before it expires
- @(posedge clk);
+ @(posedge eth_clk);
- SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters
- repeat (10)
- @(posedge clk);
+ repeat (1000)
+ @(posedge sys_clk);
+ SendPacket_to_fifo36(32'hA0B0C0D0,10); // This packet gets dropped by the filters
+ repeat (1000)
+ @(posedge sys_clk);
- SendPacketFromFile_ll8(60,0,0); // The rest are valid packets
+ SendPacket_to_fifo36(32'hAABBCCDD,100); // This packet gets dropped by the filters
+ repeat (10)
+ @(posedge sys_clk);
+/*
+ SendPacketFromFile_f36(60,0,0); // The rest are valid packets
repeat (10)
@(posedge clk);
- SendPacketFromFile_ll8(61,0,0);
+ SendPacketFromFile_f36(61,0,0);
repeat (10)
@(posedge clk);
- SendPacketFromFile_ll8(62,0,0);
+ SendPacketFromFile_f36(62,0,0);
repeat (10)
@(posedge clk);
- SendPacketFromFile_ll8(63,0,0);
+ SendPacketFromFile_f36(63,0,0);
repeat (1)
@(posedge clk);
- SendPacketFromFile_ll8(64,0,0);
+ SendPacketFromFile_f36(64,0,0);
repeat (10)
@(posedge clk);
- SendPacketFromFile_ll8(59,0,0);
+ SendPacketFromFile_f36(59,0,0);
repeat (1)
@(posedge clk);
- SendPacketFromFile_ll8(58,0,0);
+ SendPacketFromFile_f36(58,0,0);
repeat (1)
@(posedge clk);
- SendPacketFromFile_ll8(100,0,0);
+ SendPacketFromFile_f36(100,0,0);
repeat (1)
@(posedge clk);
- SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns
+ SendPacketFromFile_f36(200,150,30); // waiting 14 empties the fifo, 15 underruns
repeat (1)
@(posedge clk);
- SendPacketFromFile_ll8(100,0,30);
- #10000 $finish;
+ SendPacketFromFile_f36(100,0,30);
+ */
+ #100000 $finish;
end
// Force a CRC error
initial
begin
#90000;
- @(posedge clk);
+ @(posedge eth_clk);
FORCE_DAT_ERR <= 8'h10;
- @(posedge clk);
+ @(posedge eth_clk);
FORCE_DAT_ERR <= 8'h00;
end
@@ -168,12 +158,12 @@ module simple_gemac_wrapper_tb;
initial
begin
#116000;
- @(posedge clk);
+ @(posedge eth_clk);
FORCE_ERR <= 1;
- @(posedge clk);
+ @(posedge eth_clk);
FORCE_ERR <= 0;
end
-
+/*
// Cause receive fifo to fill, causing an RX overrun
initial
begin
@@ -184,7 +174,7 @@ module simple_gemac_wrapper_tb;
@(posedge clk);
rx_ll_dst_rdy2 <= 1;
end
-
+ */
// Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
// Still need to test: CRC errors on Pause Frames, MDIO, wishbone
@@ -205,7 +195,7 @@ module simple_gemac_wrapper_tb;
wb_we <= 0;
end
endtask // WishboneWR
-
+ /*
always @(posedge clk)
if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
begin
@@ -215,5 +205,5 @@ module simple_gemac_wrapper_tb;
if(rx_ll_eof2 & ~rx_ll_sof2)
$display("RX-PKT-END %d",$time);
end
-
+ */
endmodule // simple_gemac_wrapper_tb
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 21:49:33 +0000