diff options
Diffstat (limited to 'serdes')
| -rw-r--r-- | serdes/serdes.v | 16 | ||||
| -rw-r--r-- | serdes/serdes_rx.v | 44 | ||||
| -rw-r--r-- | serdes/serdes_tx.v | 39 |
3 files changed, 35 insertions, 64 deletions
diff --git a/serdes/serdes.v b/serdes/serdes.v index 8429b8fd9..17049bfe6 100644 --- a/serdes/serdes.v +++ b/serdes/serdes.v @@ -7,12 +7,10 @@ module serdes (input clk, input rst, // TX side output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb, - input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, - input rd_sop_i, input rd_eop_i, + input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i, // RX side input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, - output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, - input wr_ready_i, input wr_full_i, + output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i, output [15:0] tx_occupied, output tx_full, output tx_empty, output [15:0] rx_occupied, output rx_full, output rx_empty, @@ -29,8 +27,7 @@ module serdes serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx (.clk(clk),.rst(rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o), - .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i), + .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i), .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent), .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty), .debug(debug_tx) ); @@ -38,8 +35,7 @@ module serdes serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx (.clk(clk),.rst(rst), .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o), - .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i), + .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i), .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), .serdes_link_up(serdes_link_up), .debug(debug_rx) ); @@ -55,13 +51,13 @@ module serdes //assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] }; //assign debug = debug_rx; - assign debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, rd_read_o, rd_done_o, rd_sop_i, rd_eop_i }, + assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]}, { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb}, { ser_t[15:8] }, { ser_t[7:0] } }; assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */ - { wr_write_o, wr_error_o, wr_ready_i, wr_done_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, + { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, { ser_r[15:8] }, { ser_r[7:0] } }; endmodule // serdes diff --git a/serdes/serdes_rx.v b/serdes/serdes_rx.v index 8c488d7d7..aaca94ff1 100644 --- a/serdes/serdes_rx.v +++ b/serdes/serdes_rx.v @@ -32,12 +32,10 @@ module serdes_rx input ser_rkmsb, output [31:0] wr_dat_o, - output wr_write_o, - output wr_done_o, - output wr_error_o, + output [3:0] wr_flags_o, input wr_ready_i, - input wr_full_i, - + output wr_ready_o, + output [15:0] fifo_space, output xon_rcvd, output xoff_rcvd, @@ -83,6 +81,7 @@ module serdes_rx wire [15:0] nextCRC; reg write_d; + wire rst_rxclk; oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); /* @@ -311,34 +310,21 @@ module serdes_rx .wr_data_count() ); assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - {{(16-FIFOSIZE){1'b0}},level}; - assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level }; - assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain - assign fifo_empty = empty; + assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level }; + assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain + assign fifo_empty = empty; `endif // `ifdef XILFIFO // Internal FIFO to Buffer interface - reg xfer_active; - - always @(posedge clk) - if(rst) - xfer_active <= 0; - else if(xfer_active & ~empty & (eop_o | wr_full_i | error_o)) - xfer_active <= 0; - else if(wr_ready_i & sop_o) - xfer_active <= 1; - - assign read = (xfer_active | ~sop_o) & ~empty; - - assign wr_write_o = xfer_active & ~empty; - assign wr_done_o = eop_o & ~empty & xfer_active; - //assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o & ~empty)|error_o); - assign wr_error_o = xfer_active & ~empty & error_o; - - assign wr_dat_o = line_o; - - wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) || + assign read = wr_ready_i & wr_ready_o; + assign wr_ready_o = ~empty; + assign wr_dat_o = line_o; + assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o }; + + wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) || ({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r})); + reg [3:0] slu_reg; always @(posedge clk) @@ -348,6 +334,6 @@ module serdes_rx always @(posedge clk) serdes_link_up <= &slu_reg[3:1]; - assign debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i, state[2:0] }; + assign debug = { full, empty, odd, sop_i, eop_i, error_i, state[2:0] }; endmodule // serdes_rx diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index fa4abe5df..b6f19370e 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -33,11 +33,9 @@ module serdes_tx // TX Stream Interface input [31:0] rd_dat_i, - output rd_read_o, - output rd_done_o, - output rd_error_o, - input rd_sop_i, - input rd_eop_i, + input [3:0] rd_flags_i, + output rd_ready_o, + input rd_ready_i, // Flow control interface input inhibit_tx, @@ -82,33 +80,24 @@ module serdes_tx wire sop_o, eop_o, write, full, read, empty; wire [31:0] data_o; reg xfer_active; + + wire rd_sop_i = rd_flags_i[0]; + wire rd_eop_i = rd_flags_i[1]; + wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo (.clk(clk),.rst(rst),.clear(0), .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full), .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty), .space(), .occupied(fifo_occupied) ); - assign fifo_full = full; - assign fifo_empty = empty; - - // Buffer interface to internal FIFO - always @(posedge clk) - if(rst) - xfer_active <= 0; - else if(rd_eop_i & ~full) // In case we can't store last line right away - xfer_active <= 0; - else if(rd_sop_i) - xfer_active <= 1; - - assign write = xfer_active & ~full; - - assign rd_read_o = write; - assign rd_done_o = 0; // Always take everything we're given - assign rd_error_o = 0; // No chance for errors anticipated - - - // FIXME Implement flow control + assign fifo_full = full; + assign fifo_empty = empty; + + assign write = rd_ready_i & rd_ready_o; + assign rd_ready_o = ~full; + + // FIXME Implement flow control reg [15:0] second_word; reg [33:0] pipeline; |