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-rw-r--r--serdes/serdes.v16
-rw-r--r--serdes/serdes_rx.v111
-rw-r--r--serdes/serdes_tx.v51
3 files changed, 50 insertions, 128 deletions
diff --git a/serdes/serdes.v b/serdes/serdes.v
index 8429b8fd9..17049bfe6 100644
--- a/serdes/serdes.v
+++ b/serdes/serdes.v
@@ -7,12 +7,10 @@ module serdes
(input clk, input rst,
// TX side
output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb,
- input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
- input rd_sop_i, input rd_eop_i,
+ input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i,
// RX side
input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
- output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
- input wr_ready_i, input wr_full_i,
+ output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i,
output [15:0] tx_occupied, output tx_full, output tx_empty,
output [15:0] rx_occupied, output rx_full, output rx_empty,
@@ -29,8 +27,7 @@ module serdes
serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
(.clk(clk),.rst(rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
- .rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
- .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
+ .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i),
.inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent),
.fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
.debug(debug_tx) );
@@ -38,8 +35,7 @@ module serdes
serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
(.clk(clk),.rst(rst),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
- .wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o),
- .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
+ .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i),
.fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
.fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
.serdes_link_up(serdes_link_up), .debug(debug_rx) );
@@ -55,13 +51,13 @@ module serdes
//assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
//assign debug = debug_rx;
- assign debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, rd_read_o, rd_done_o, rd_sop_i, rd_eop_i },
+ assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]},
{ debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
{ ser_t[15:8] },
{ ser_t[7:0] } };
assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
- { wr_write_o, wr_error_o, wr_ready_i, wr_done_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
+ { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
{ ser_r[15:8] },
{ ser_r[7:0] } };
endmodule // serdes
diff --git a/serdes/serdes_rx.v b/serdes/serdes_rx.v
index 8c488d7d7..afefccaa1 100644
--- a/serdes/serdes_rx.v
+++ b/serdes/serdes_rx.v
@@ -32,12 +32,10 @@ module serdes_rx
input ser_rkmsb,
output [31:0] wr_dat_o,
- output wr_write_o,
- output wr_done_o,
- output wr_error_o,
+ output [3:0] wr_flags_o,
input wr_ready_i,
- input wr_full_i,
-
+ output wr_ready_o,
+
output [15:0] fifo_space,
output xon_rcvd, output xoff_rcvd,
@@ -72,7 +70,7 @@ module serdes_rx
reg [31:0] line_i;
reg sop_i, eop_i, error_i;
- wire error_o, sop_o, eop_o, write, read, empty, full;
+ wire error_o, sop_o, eop_o, write;
reg [15:0] halfline;
reg [8:0] holder;
wire [31:0] line_o;
@@ -83,14 +81,11 @@ module serdes_rx
wire [15:0] nextCRC;
reg write_d;
+ wire rst_rxclk;
+ wire have_space;
+
oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk));
- /*
- ss_rcvr #(.WIDTH(18)) ss_rcvr
- (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
- .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data),
- .clock_present());
- */
assign even_data = {ser_rkmsb,ser_rklsb,ser_r};
always @(posedge ser_rx_clk)
@@ -172,7 +167,7 @@ module serdes_rx
if(chosen_data[17:16] == 0)
begin
line_i <= {chosen_data[15:0],halfline};
- if(full) // No space to write to! Should have been avoided by flow control
+ if(~have_space) // No space to write to! Should have been avoided by flow control
state <= ERROR;
else
begin
@@ -205,7 +200,7 @@ module serdes_rx
if(chosen_data[17:16] == 0)
begin
line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline};
- if(full) // No space to write to!
+ if(~have_space) // No space to write to!
state <= ERROR;
else
begin
@@ -221,7 +216,7 @@ module serdes_rx
CRC_CHECK :
if(chosen_data[17:0] == {2'b00,CRC})
begin
- if(full)
+ if(~have_space)
state <= ERROR;
else
begin
@@ -237,7 +232,7 @@ module serdes_rx
ERROR :
begin
error_i <= 1;
- if(~full)
+ if(have_space)
state <= IDLE;
end
DONE :
@@ -264,81 +259,25 @@ module serdes_rx
else write_d <= write_pre;
// Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
- assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
-
+ assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK));
-//`define CASC 1
-`define MYFIFO 1
-//`define XILFIFO 1
-
-`ifdef CASC
- cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
- .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
- .space(fifo_space),.occupied(fifo_occupied) );
- assign fifo_full = full;
- assign fifo_empty = empty;
-`endif
-
-`ifdef MYFIFO
- wire [FIFOSIZE-1:0] level;
- fifo_2clock_casc #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo
+ fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
(.arst(rst),
- .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
- .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
- .level_rclk(level) );
- assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} -
- {{(16-FIFOSIZE){1'b0}},level};
- assign fifo_occupied = { {(16-FIFOSIZE){1'b0}} ,level};
- assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain
- assign fifo_empty = empty;
-`endif
+ .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}),
+ .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space),
+ .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}),
+ .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) );
-`ifdef XILFIFO
- wire [FIFOSIZE-1:0] level;
- fifo_generator_v4_1 ser_rx_fifo
- (.din({error_i,sop_i,eop_i,line_i}),
- .rd_clk(clk),
- .rd_en(read),
- .rst(rst),
- .wr_clk(ser_rx_clk),
- .wr_en(write),
- .dout({error_o,sop_o,eop_o,line_o}),
- .empty(empty),
- .full(full),
- .rd_data_count(level),
- .wr_data_count() );
- assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} -
- {{(16-FIFOSIZE){1'b0}},level};
- assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level };
- assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain
- assign fifo_empty = empty;
-`endif // `ifdef XILFIFO
-
+ assign fifo_full = ~have_space; // Note -- in the wrong clock domain
+ assign fifo_empty = ~wr_ready_o;
// Internal FIFO to Buffer interface
- reg xfer_active;
-
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(xfer_active & ~empty & (eop_o | wr_full_i | error_o))
- xfer_active <= 0;
- else if(wr_ready_i & sop_o)
- xfer_active <= 1;
-
- assign read = (xfer_active | ~sop_o) & ~empty;
-
- assign wr_write_o = xfer_active & ~empty;
- assign wr_done_o = eop_o & ~empty & xfer_active;
- //assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o & ~empty)|error_o);
- assign wr_error_o = xfer_active & ~empty & error_o;
-
- assign wr_dat_o = line_o;
-
- wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) ||
+ assign wr_dat_o = line_o;
+ assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o };
+
+ wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) ||
({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r}));
+
reg [3:0] slu_reg;
always @(posedge clk)
@@ -348,6 +287,6 @@ module serdes_rx
always @(posedge clk)
serdes_link_up <= &slu_reg[3:1];
- assign debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i, state[2:0] };
+ assign debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] };
endmodule // serdes_rx
diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v
index fa4abe5df..c74414e92 100644
--- a/serdes/serdes_tx.v
+++ b/serdes/serdes_tx.v
@@ -33,11 +33,9 @@ module serdes_tx
// TX Stream Interface
input [31:0] rd_dat_i,
- output rd_read_o,
- output rd_done_o,
- output rd_error_o,
- input rd_sop_i,
- input rd_eop_i,
+ input [3:0] rd_flags_i,
+ output rd_ready_o,
+ input rd_ready_i,
// Flow control interface
input inhibit_tx,
@@ -79,36 +77,25 @@ module serdes_tx
reg [3:0] wait_count;
// Internal FIFO, size 9 is 2K, size 10 is 4K bytes
- wire sop_o, eop_o, write, full, read, empty;
+ wire sop_o, eop_o;
wire [31:0] data_o;
- reg xfer_active;
-
- cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
- .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty),
+
+ wire rd_sop_i = rd_flags_i[0];
+ wire rd_eop_i = rd_flags_i[1];
+ wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused
+
+ wire have_data, empty;
+ fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
+ (.clk(clk),.reset(rst),.clear(0),
+ .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
+ .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
.space(), .occupied(fifo_occupied) );
- assign fifo_full = full;
- assign fifo_empty = empty;
-
- // Buffer interface to internal FIFO
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(rd_eop_i & ~full) // In case we can't store last line right away
- xfer_active <= 0;
- else if(rd_sop_i)
- xfer_active <= 1;
-
- assign write = xfer_active & ~full;
-
- assign rd_read_o = write;
- assign rd_done_o = 0; // Always take everything we're given
- assign rd_error_o = 0; // No chance for errors anticipated
-
- // FIXME Implement flow control
+ assign fifo_full = ~rd_ready_o;
+ assign empty = ~have_data;
+ assign fifo_empty = empty;
+ // FIXME Implement flow control
reg [15:0] second_word;
reg [33:0] pipeline;
@@ -193,7 +180,7 @@ module serdes_tx
CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
- assign debug = { 26'd0, full, empty, xfer_active, state[2:0] };
+ assign debug = { 28'd0, state[2:0] };
endmodule // serdes_tx
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 21:36:58 +0000